Abstract: Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed.

Abstract: Subject matter disclosed herein relates to enhancing data storage density of a memory device.

Abstract: The present invention discloses a method including: writing a phase change material from a high RESET state to a weakened RESET state with a first step; writing the phase change material from the weakened RESET state to a SET state with a second step, the second step having a lower current than the first step; verifying a parameter of the phase change material wherein if the parameter is higher than a target for a SET state, then repeating the writing with the first step, the writing with the second step, and the verifying until the parameter is lower than the target wherein a current for the first step is decreased by a decrement with each iteration without becoming lower than a current for the second step.

Abstract: An electrostatic discharge protection circuit may include ovonic threshold switches that have a holding voltage greater than an input voltage normally received from a pad. As a result, the ovonic threshold switches provide a low resistance state to shunt current from the pad when an electrostatic discharge protection event occurs and, otherwise, present an off device during normal circuit operations.

Abstract: A phase change memory including a threshold device, such as an ovonic threshold switch, and a storage device may be read. Reading the cell may involve applying a first voltage to a selected cell and then a second voltage, lower than the first voltage. The first voltage may be sufficient to threshold the ovonic threshold switch if the storage device is in the set state.

Abstract: A memory device including a plurality of memory cells being arranged in a matrix having a plurality of rows and a plurality of columns. Each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The memory device further including a plurality of row lines each one for selecting the memory cells of a corresponding row and a plurality of column lines each one for selecting the memory cells of a corresponding column. The memory device further includes for each line among the row lines and/or the column lines a respective set of local lines each one for selecting a group of memory cells of the corresponding line, and a respective set of selection elements each one for selecting a corresponding local line of the set in response to the selection of the respective line.

Abstract: One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.

Abstract: A resistive memory cell may be composed of four stacked layers. Each layer may be sandwiched by electrodes. Connections may be formed from each of four directions around the stack, for example, aligned with each of four edges where the resistive layers are rectangular.

Abstract: An electrostatic discharge protection circuit may include ovonic threshold switches that have a holding voltage greater than an input voltage normally received from a pad. As a result, the ovonic threshold switches provide a low resistance state to shunt current from the pad when an electrostatic discharge protection event occurs and, otherwise, present an off device during normal circuit operations.

Abstract: A self-aligned phase change memory may be formed by blanket depositing a number of layers and then using patterning techniques to define the individual cells. In one embodiment, a layer of phase change material may be blanket deposited over a lower electrode material. The structure may then be patterned and etched to form a plurality of spaced, parallel elongate first strips. Those strips may then be covered with a filler material, planarized, and then patterned again in a transverse direction to form a plurality of transverse, spaced, parallel second strips. The resulting structure then has singulated phase change material with connections in at least one of the row or column direction. The singulated the phase change material is self-aligned to underlying and overlying electrodes.

Abstract: A phase change memory may be formed with an upper electrode self-aligned to a phase change memory element. In some embodiments, patterning techniques may be used to form the elements of the memory. The memory element may be formed as a sidewall spacer formed on both opposed sides of an elongate strip of material. The resulting elongate strip of phase change memory element material may then be singulated in the same etching step that forms the upper electrodes extending in the column direction. Thus, the memory elements may be singulated in the row direction, while, at the same time, the top electrodes are defined to extend continuously in the column direction.

Abstract: An ovonic threshold switch may be used to form an anti-fuse. As manufactured, the fuse may be in its amorphous state, as is conventional for ovonic threshold switches. However, when exposed to a sufficient voltage under appropriate circumstances, the anti-fuse may fuse in a more conductive state. As fused, the cell may exhibit both crystalline characteristics in the chalcogenide material and mixing of electrode material into the chalcogenide, rendering the anti-fuse in a generally irreversible conductive or crystalline state.

Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.

Abstract: A phase change memory including a threshold device, such as an ovonic threshold switch, and a storage device may be read. Reading the cell may involve applying a first voltage to a selected cell and then a second voltage, lower than the first voltage. The first voltage may be sufficient to threshold the ovonic threshold switch if the storage device is in the set state.

Abstract: A metal oxide semiconductor varactor may be formed with HALO implants regions having an opposite polarity from the polarity of the well of the varactor. The HALO implant regions can be angled away from the source and drain. The HALO implant regions can stop the depletion from continuing as the bias voltage applied to the gate continues to increase. Stopping that depletion can create a constant capacitance when the varactor is in a depletion bias.

Abstract: An MOS varactor may be formed without tip implants or HALO implants. As a result, parasitic resistance may be reduced, jitter may be improved, and the quality factor may be increased, as well as the tunable range of the varactor.

Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.

Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.

Abstract: A transistor comprising a gate, a channel beneath the gate and separated from the gate by an insulator, a source adjacent to the channel on a first side of the gate, a drain adjacent to the channel on a second side of the gate, doped extension regions into the channel from the source and the drain that underlap the gate, and insulating spacers adjacent to sidewalls of the gate that overlap the extension regions. The insulating spacers may be used to align the doped extension regions, offset the extension regions from the gate, and reduce Miller capacitance and standby leakage current.

Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.