Abstract: A system includes a current sense amplifier to receive an input voltage based on a sense current provided to load circuitry. The current sense amplifier is configured to generate an output voltage from the input voltage based, at least in part, on one or more reconfigurable characteristics of the current sense amplifier. The system also includes a microcontroller to compare the output voltage from the current sense amplifier to one or more programmable thresholds. The microcontroller is configured to direct a current controller to regulate the sense current provided to the load circuitry according to the comparison.

Abstract: A system includes a current sense amplifier to receive an input voltage based on a sense current provided to load circuitry. The current sense amplifier is configured to generate an output voltage from the input voltage based, at least in part, on one or more reconfigurable characteristics of the current sense amplifier. The system also includes a microcontroller to compare the output voltage from the current sense amplifier to one or more programmable thresholds. The microcontroller is configured to direct a current controller to regulate the sense current provided to the load circuitry according to the comparison.

Abstract: A data interface is provided that can de-skew data signals by taking into account different skewing effects on each data signal. The data interface can be used, for example, in a communication system and can be configured to operate in one of three possible modes of operation. In the first mode, de-skewing is fixed prior to the sample logic. In the second mode, de-skewing is periodically changed automatically as the amount of skew changes based on training signals that are periodically sent into the data interface. The combination of the data phase count and the positive and negative clock width pulse counts will then determine where the final transition or edge of each data signal is to be placed within a bit. The third mode of operation involves an override or programmatic modification of the second mode of operation based on values stored in a register.

Abstract: The system and method facilitates the transmission of relatively high voltage signals via a thin oxide gate CMOS device without an excessively detrimental electric field build up across the thin oxide layers forming a gate in a CMOS device. The high voltage CMOS thin oxide gate system and method provides a degradation repression bias voltage signal to the thin oxide gate of the CMOS device. The degradation repression bias voltage signal establishes a differential voltage potential between the source and drain components of the thin oxide gate output CMOS device and the gate component of the thin oxide gate output CMOS device. The degradation repression bias voltage signal is maintained at a level that prevents that excessively detrimental electric field stresses are not induced in oxide layers that form the thin oxide gate in the output CMOS device.

Abstract: The present invention includes differential devices and methods of protecting a semiconductor device. One aspect of the present invention provides a differential device adapted to be coupled to a ground connection, the differential device comprising: a first interconnect; a second interconnect; a common diffusion region; a first MOS device coupled with the common diffusion region and the first interconnect; a second MOS device coupled with the common diffusion region and the second interconnect; and a tail MOS device coupled with the common diffusion region and adapted to be coupled to a ground connection.

Abstract: The present invention includes differential devices and methods of protecting a semiconductor device. One aspect of the present invention provides a differential device adapted to be coupled to a ground connection, the differential device comprising: a first interconnect; a second interconnect; a common diffusion region; a first MOS device coupled with the common diffusion region and the first interconnect; a second MOS device coupled with the common diffusion region and the second interconnect; and a tail MOS device coupled with the common diffusion region and adapted to be coupled to a ground connection.

Abstract: An I/O buffer with minimized footprint; which is less susceptible to voltage spikes caused by switching noise, and which is adapted for used in a separate power bus arrangement. The buffer minimizes voltage spikes caused by switching noise by replacing the single large current surge that occurs during switching with smaller current surges at different times. This is accomplish by having two different drivers for the transitional and holding phases: a Transient Switching Circuit (TSC) and a Logic Holding Circuit (LHC). Generally, the TSC is operational to cause a change in the output signal when there is a change in the input signal. Conversely, the LHC is operational subsequent to the logic transition occurrence at the input signal to bring the output signal to the rail voltage.

Abstract: An input/output circuit communicates an external input signal to an internal signal and converts an internal signal to an external output signal. In one embodiment, the input/output circuit has a power supply terminal, and an input terminal that is coupled to an output terminal via a conductor. A pull-up circuit is coupled to the power supply terminal and the conductor, and includes a PMOS transistor having an N-well, where the pull-up circuit is configured to selectively pull-up the output signal. A pull-down circuit is coupled to a ground terminal and the conductor, and is configured to selectively pull-down the output signal.

Abstract: An I/O buffer is provided that is noise-isolated, i.e., less susceptible to the effect of switching noise. In particular, a noise isolated I/O buffer includes an output terminal, a transient switching circuit connected to first power and ground voltage sources, to a logic input signal and to the output terminal, and a logic holding circuit connected to second power and ground voltage sources separate from the first power ground voltage sources, to the logic input signal and to the output terminal. The transient switching circuit causes a logic level of the output terminal to be switched responsive to a change in the input signal. The logic holding circuit causes the logic level of the output terminal to be maintained in the absence of a change in the input signal. In the absence of a change in the input signal, the transient switching circuit may be turned off, therefore presenting a high impedance to the first power and ground voltage sources.

Abstract: An I/O buffer is provided that is noise-isolated, i.e., less susceptible to the effect of switching noise. In particular, a noise isolated I/O buffer includes an output terminal, a transient switching circuit connected to first power and ground voltage sources, to a logic input signal and to the output terminal, and a logic holding circuit connected to second power and ground voltage sources separate from the first power ground voltage sources, to the logic input signal and to the output terminal. The transient switching circuit causes a logic level of the output terminal to be switched responsive to a change in the input signal. The logic holding circuit causes the logic level of the output terminal to be maintained in the absence of a change in the input signal. In the absence of a change in the input signal, the transient switching circuit may be turned off, therefore presenting a high impedance to the first power and ground voltage sources.

Abstract: A circuit buffers output in an integrated circuit. The circuit includes a circuit input, a circuit output, a power signal, a ground signal, a first transistor, a second transistor, a third transistor, a fourth transistor, variable resistance means, and control means. The variable resistance means is connected between the source of the first transistor and the drain of the second transistor. The variable resistance provides one of a first impedance and a second impedance between the source of the first transistor and drain of the second transistor in response to a control signal. The control means is connected to the control input means of the variable resistance means. After a voltage level transition on the circuit input and during a resulting voltage level transition on the circuit output, in response to the control means, the variable resistance means first provides the first impedance and then provides the second impedance between the source of the first transistor and drain of the second transistor.