Abstract: The invention relates to spherical and magnetic silicagel particles which are provided with an increased surface by incorporating SiO2 colloids and produced by a method for inverse dispersion cross-linking of silica sols. The addition of certain metallic oxides to said silica sols and a subsequent tempering make it possible to obtain silicagel particles which exhibit increased nucleic acid binding properties and are used for separating a nucleic acid and isolating biomolecules.

Abstract: In order to further develop a circuit arrangement (100) as well as a method of processing data to be protected against unauthorized access by means of encryption or decryption, by means of which method the data are stored in at least two memory modules (10, 12) in such way that a flexible configuration of any memory parts as main memory or redundancy memory is enabled, it is proposed to provide at least one real-time configurable redundancy concept for the memory modules (10, 12), by which the data can be stored redundantly in physically separate memory modules (10, 12).

Abstract: In an integrated-circuit chip having intercommunicating modular functional units of electrical circuits, wired transmission of sensitive information signals between the functional units of the electrical circuits involves generating a reference signal and coding the sensitive information signals, after being emitted by a generating functional unit in the chip, with the reference signal to disguise the sensitive information represented by the sensitive information signals. The coded sensitive information signals are decoded with the reference signal before the sensitive information signals are received by a processing functional unit in the chip. At least one signal of the reference signal and the decoded sensitive information signals are monitored, and a hacker attack is identified in response to a determination that the decoded sensitive information signal is other than a plausible signal.

Abstract: The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding computer-readable storage medium, which may be used in particular to speed up writing or programming processes in NV code memories of microcontrollers, such as for example smart card controllers. The method consists in extending the instruction set of the controller by so-called MOVCWR (move code write) instructions, which make it possible to write a defined data word (byte) to a defined destination address within an NV code memory. The data word (byte) is here written to the correct position of the cache page register of the respective NV memory and the page address pointer register of the memory is updated with the associated page address. If an MMU (memory management unit) is present, this MOVCWR writing to the cache page register takes place, like MOVC reading or code fetch, under the control of this MMU.

Abstract: The present invention may relate generally to a circuit for converting a first digital signal having a first sample rate to second digital signal having a second sample rate. The circuit may comprise a cascaded integration-comb filter and a fractional sample rate converter. The fractional sample rate converter may be configured to perform fractional sample rate conversion. A first of the cascaded integrator-comb filter and the fractional sample rate converter may be configured to receive the first signal having the first sample rate and to generate a third digital signal having a third sample rate different from the first and second sample rates. A second of the cascaded integrator-comb filter and the fractional sample rate converter may be configured to receive the third signal having the third sample rate and to generate the second signal having the second sample rate.

Abstract: The invention relates to a reinforcing element for an article of clothing, in particular for a goalkeeper glove, that allows a bending in a first direction, but resists bending in a second direction. The reinforcing element includes at least one bending area that has a curvature with a shape that allows bending of the reinforcing element in the first direction and blocks a bending of the reinforcing element in the second direction.

Abstract: The invention relates to biocompatible, thermosensitive polymers that can be heated, with the aid of a high-frequency magnetic alternating field, by encapsulating magnetic and/or metallic colloids or magnetic nanoparticles. As a result of the inductive heating of the polymer matrix, physical structure changes are triggered in the polymer matrix that lead to the bioactive substances encapsulated in the matrix being released within a short period of time. This “stimulus-response” principle is employed for the production of controllable drug depots, contrast-intensifying media for NMR diagnostics or manipulable micro-tools, as media for blocking blood vessels and as controllable porogens in the production of membranes.

Abstract: The invention relates to spherical and magnetic silicagel particles which are provided with an increased surface by incorporating SiO2 colloids and produced by a method for inverse dispersion cross-linking of silica sols. The addition of certain metallic oxides to said silica sols and a subsequent tempering make it possible to obtain silicagel particles which exhibit increased nucleic acid binding properties and are used for separating a nucleic acid and isolating biomolecules.

Abstract: The invention relates to a method and an arrangement for the verification of NV fuses as well as to a corresponding computer program product and to a corresponding computer-readable storage medium which can be used notably for the detection of attacks on the smart card security which modify EEPROM contents and hence also the contents of EEPROM fuses. During the reset phase the fuses are read from the EEPROM. The fuse values successively read out are then automatically verified. One possible implementation is, for example, to load the fuse values read out into a signature register, followed by comparison with a reference value. Appropriate security measures can be activated should the automatic verification indicate an error, for example, due to unauthorized modification of a fuse or attack on the boot operation.

Abstract: The invention relates to a reinforcing element for an article of clothing, in particular for a goalkeeper glove, that allows a bending in a first direction, but resists bending in a second direction. The reinforcing element includes at least one bending area that has a curvature with a shape that allows bending of the reinforcing element in the first direction and blocks a bending of the reinforcing element in the second direction.

Abstract: In the programming of a microcontroller (100) carried out in at least one machine-dependent assembly language in which the assembler commands, with the exception of conditional program branches, are executable essentially independently of data,—in case of a fulfilled branch condition, for example, at least one fulfilled status flag, at least one program counter (10) is loadable with a new address and/or a new value, and—in case of an unfulfilled branch condition, for example, at least one unfulfilled status flag, the instruction is ended.

Abstract: In order to further develop a microcontroller (100) the programming of which is carried out in at least one machine-dependent assembler language in which the assembler commands, with the exception of conditional program jumps or branches, can be executed in essence independently of data, together with a method for processing the programming of the microcontroller (100) carried out in at least one machine-dependent assembler language, in such a way that the program running on the microcontroller (100) is entirely secret and unpredictable, i.e. is not reproducible, for an external observer, it is proposed that the program jumps or branches are executed—in dependence on the state of at least one random number generator (10) and/or—independently of the internal state of the programming of the microcontroller (100).

Abstract: A digital microelectronic circuit comprises a clocked data-processing unit (1) and a converting unit (2) which reads in data present at the output of the data-processing unit, performs a predetermined converting operation on the data and passes on the converted data. The converting unit is realized in an asynchronous logic circuit, such that the period of time for performing the converting operation is shorter than the shortest time interval to the next change of the data present at the output of the data-processing unit. In this way, fast, serial synchronous processes can be parallelized from the point of view of the slow synchronous system in synchronous systems which are slow relative thereto by using asynchronous logics, without a further high-frequency clock system being required.

Abstract: In order to develop an electronic memory component or memory module (100), having at least one memory cell area (10) in which physical states (P) representing regular data are mapped by means of at least one mapping function (A) that describes at least one error correction code, for example at least one Hamming code, and also a method of operating at least one electronic memory component or memory module (100) of the abovementioned type, such that on the one hand the error detection probability is considerably increased and on the other hand unwritten memory blocks can be reliably distinguished from memory blocks that have already been written to once before, it is proposed that at least one further physical state in the form of at least one exceptional or special state (L, S) in the error correction code can be detected, encoded and/or indicated by means of the mapping function (A).

Abstract: Fuses that selectively disable functional blocks of a circuit are arranged in a multistage structure, wherein if any fuse element in the multistage structure permanently switches off a part of the circuit, no other fuse element in the multistage structure can affect the switching off of the part. Master fuses are provided to selectively disable corresponding stages of the multistage structure. Preferably, the master fuses are arranged in a hierarchy, so that a master fuse at a higher level of the hierarchy selectively disables all of the stages at lower levels of the hierarchy.

Abstract: The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding computer-readable storage medium, which may be used in particular to speed up writing or programming processes in NV code memories of microcontrollers, such as for example smart card controllers. The method consists in extending the instruction set of the controller by so-called MOVCWR (move code write) instructions, which make it possible to write a defined data word (byte) to a defined destination address within an NV code memory. The data word (byte) is here written to the correct position of the cache page register of the respective NV memory and the page address pointer register of the memory is updated with the associated page address. If an MMU (memory management unit) is present, this MOVCWR writing to the cache page register takes place, like MOVC reading or code fetch, under the control of this MMU.

Abstract: A signal interpolator comprises a fractional interpolator and a numeric controlled oscillator. The numeric controlled oscillator may generate a control signal for controlling the fractional interpolator. The numeric controlled oscillator generally comprises a register, a modulo-M device, and an adder. The register may hold a count value, and the modulo-M device may apply a modulo-M function to the count value to generate the control signal therefrom. The adder may add an increment value to the modulo-M signal from the modulo-M device, to update the count value in the register.

Abstract: In a microcontroller (100) the command decoder (15) has access to at least one memory (14). The command decoder may thus be adapted to decode at least one conditional command, while the result of decoding the conditional command is dependent on the contents of said memory (14). The microcontroller according to the invention thus provides the possibility of considerably reducing the programming effort so that both the system performance and the code density can be significantly increased with a small additional number of hardware components.

Abstract: The invention relates to a method and an arrangement for controlling access to EEPROMs' and to a corresponding computer software product and a corresponding computer-readable storage medium, which can in particular be used to prevent the unauthorized manipulation of EEPROMs. Specifically, it is possible by using the invention to stop the unauthorized use of totally erased EEPROMs on smart-card controllers. EEPROM fuses that, depending on the application, comprise one or more bits, are used in the continuing course of operation of a controller, to permit or forbid security-related functions. Provision is made as part of the invention for EEPROM fuses to be used to permit writing to the EEPROM only if said fuse comprises a given combination of bits. Any manipulation of this fuse, such as by erasing the entire matrix for example or else by manipulating the booting process, then bars all further write accesses to the EEPROM.

Abstract: To provide an electric or electronic circuit arrangement as well as a method of detecting and/or identifying and/or recording at least an access violation, particularly at least a memory access violation, in a microcontroller provided particularly for a chip card or smart card, with which the source causing this access violation (referred to as break source) as well as the code address occurring upon this violation can be detected and/or identified and/or recorded when an access violation occurs during the program run, the circuit arrangement comprises at least a memory unit; at least an interface unit assigned to the memory unit; at least a processor unit connected to the memory unit particularly via the interface unit for executing instruction codes.