Patents by Inventor Dev Sharma
Dev Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9612300Abstract: An object-based approach is used to initialize the magnetic field inhomogeneity estimation for chemical species separation, such as water-fat separation, and other imaging applications. For example, a susceptibility distribution in the subject being imaged is estimated from images reconstructed from single-echo or multi-echo k-space data and used to initialize the magnetic field inhomogeneity estimation. This approach can be applied to any complex-based chemical shift encoded chemical species separation technique and to other imaging applications, such as susceptibility-weighted imaging and quantitative susceptibility mapping. The field map can also be used to correct for image distortions and to generate magnetic field shimming values.Type: GrantFiled: November 25, 2013Date of Patent: April 4, 2017Assignee: Wisconsin Alumni Research FoundationInventors: Samir Dev Sharma, Nathan Samuel Artz, Scott Brian Reeder
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Publication number: 20150145514Abstract: An object-based approach is used to initialize the magnetic field inhomogeneity estimation for chemical species separation, such as water-fat separation, and other imaging applications. For example, a susceptibility distribution in the subject being imaged is estimated from images reconstructed from single-echo or multi-echo k-space data and used to initialize the magnetic field inhomogeneity estimation. This approach can be applied to any complex-based chemical shift encoded chemical species separation technique and to other imaging applications, such as susceptibility-weighted imaging and quantitative susceptibility mapping. The field map can also be used to correct for image distortions and to generate magnetic field shimming values.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Applicant: Wisconsin Alumni Research FoundationInventors: Samir Dev Sharma, Nathan Samuel Artz, Scott Brian Reeder
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Patent number: 8756051Abstract: Communication network and method for providing communication facilities for a plurality of users. The communication network comprises an announcement generating element (14) for sending network related messages to any of the users. A further network element is connected to the announcement generating element, the further network element being arranged for determining a preferred language for a specific user (10) of the plurality of users, and sending network related messages to the specific user (10) in the preferred language.Type: GrantFiled: September 30, 2005Date of Patent: June 17, 2014Assignee: Telefonaktiebolaget L M Ericsson (Publ)Inventors: Rogier August Caspar Jospeh Noldus, Arvind Dev Sharma, Ulf Ingemar Olsson
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Patent number: 7886238Abstract: Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.Type: GrantFiled: November 28, 2006Date of Patent: February 8, 2011Assignee: Cadence Design Systems, Inc.Inventors: Harsh Dev Sharma, Rajeev Srivastava, Srinivas R. Kommoori, Bharat Bhushan, Mithunjoy Parui, Albert Lee
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Patent number: 7810063Abstract: According to various embodiments of the invention electronic circuit design information can be presented to a designer by determining an electronic circuit comprising at least two gates and by determining a distance of one gate relative to another gate in a stage. A visual indicator for the stage can be calculated based on the distances between at least two gates in the stage. The visual indicator can then be displayed. The visual indicator can be a color and the relative distance can be indicated by brightness, hue or saturation, etc. Alternatively, the visual indicator can be a pattern and the relative distance between at least two gates can be indicated by darkness of the pattern.Type: GrantFiled: February 1, 2007Date of Patent: October 5, 2010Assignee: Cadence Design Systems, Inc.Inventors: Harsh Dev Sharma, Po-chiang Albert Lee, Rajeev Srivastava, Srinivas R. Kommoori, Bharat Bhushan, Mithunjoy Parui
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Patent number: 7779201Abstract: A system and method for determining a disk ownership model to be utilized by a storage system is disclosed. The storage system and method determines the individual disk ownership of each accessible disk to the storage system. If the number of disks utilizing a first ownership model is exceeded, the storage system utilizes the first ownership model. Otherwise, the storage system utilizes a second ownership model.Type: GrantFiled: August 9, 2007Date of Patent: August 17, 2010Assignee: NetApp, Inc.Inventors: Gaurav Agarwal, Susan M. Coatney, Steven S. Watanabe, Alan L. Rowe, Samuel M. Cramer, Gautam Dev Sharma
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Patent number: 7600208Abstract: Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.Type: GrantFiled: January 31, 2007Date of Patent: October 6, 2009Assignee: Cadence Design Systems, Inc.Inventors: Harsh Dev Sharma, Rajeev Srivastava, Srivinas R. Kommoori, Bharat Bhushan, Mithunjoy Parui, Albert Lee
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Publication number: 20090018816Abstract: Communication network and method for providing communication facilities for a plurality of users. The communication network comprises an announcement generating element (14) for sending network related messages to any of the users. A further network element is connected to the announcement generating element, the further network element being arranged for determining a preferred language for a specific user (10) of the plurality of users, and sending network related messages to the specific user (10) in the preferred language.Type: ApplicationFiled: September 30, 2005Publication date: January 15, 2009Inventors: Rogier August Noldus, Arvind Dev Sharma, Ulf Ingemar Olsson
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Patent number: 7260678Abstract: A system and method for determining a disk ownership model to be utilized by a storage system is disclosed. The storage system and method determines the individual disk ownership of each accessible disk to the storage system. If the number of disks utilizing a first ownership model is exceeded, the storage system utilizes the first ownership model. Otherwise, the storage system utilizes a second ownership model.Type: GrantFiled: October 13, 2004Date of Patent: August 21, 2007Assignee: Network Appliance, Inc.Inventors: Gaurav Agarwal, Susan M. Coatney, Steven S. Watanabe, Alan L. Rowe, Samuel M. Cramer, Gautam Dev Sharma
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Patent number: 6678422Abstract: A method and apparatus for performing a multi-stage wavelet transform on a block of image data, using a smaller memory than would be required to implement an equivalent conventional multi-stage wavelet transform on the same block, and a method and apparatus for performing compression on a block of image data by performing a multi-stage wavelet transform on the block, quantizing coefficients resulting from the multi-stage wavelet transform, and performing entropy encoding on the quantized coefficients. Typically, the input image data is generated by a document scanner, and is compressed in a manner allowing fast decompression (by employing simple entropy encoding) and imposing low memory requirements.Type: GrantFiled: August 30, 2000Date of Patent: January 13, 2004Assignee: National Semiconductor CorporationInventors: Chandan Dev Sharma, Bernd Meyer
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Patent number: 6674587Abstract: The present invention relates to a method of deposition of an absorbing material upon a plastic/glass substrate by vacuum coating at an angle of inclination between 5° to 30° and using a mask on the evaporation source to produce a graded film material and a method for the preparation of graded density absorbing film useful as an antiglare optical device for protecting the eyes by reducing the glare by absorbing the light intensity falling upon it in a non-uniform fashion.Type: GrantFiled: March 30, 2001Date of Patent: January 6, 2004Assignee: Council of Scientific ResearchInventors: Deep Singh Chhabra, Parinam Krisna Rao, Bipin Dev Sharma, Dharambir Singh Dodd, Virender Singh, Sanjay Sharma
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Publication number: 20030016460Abstract: The present invention relates to a method of deposition of an absorbing material upon a plastic/glass substrate by vacuum coating at an angle of inclination between 5° to 30° and using a mask on the evaporation source to produce a graded film material and a method for the preparation of graded density absorbing film useful as an antiglare optical device for protecting the eyes by reducing the glare by absorbing the light intensity falling upon it in a non-uniform fashion.Type: ApplicationFiled: March 30, 2001Publication date: January 23, 2003Inventors: Deep Singh Chhabra, Parinam Krisna Rao, Bipin Dev Sharma, Dharambir Singh Dodd, Virender Singh, Sanjay Sharma
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Patent number: 6208907Abstract: A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.Type: GrantFiled: January 30, 1998Date of Patent: March 27, 2001Assignee: International Business Machines CorporationInventors: Christopher McCall Durham, Visweswara Rao Kodali, Douglas Ele Martin, Harsh Dev Sharma
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Patent number: 6107852Abstract: A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.Type: GrantFiled: May 19, 1998Date of Patent: August 22, 2000Assignee: International Business Machines CorporationInventors: Christopher McCall Durham, Michael Ju Hyeok Lee, Visweswara Rao Kodali, Harsh Dev Sharma
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Patent number: 6037804Abstract: A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.Type: GrantFiled: March 27, 1998Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Christopher McCall Durham, Visweswara Rao Kodali, Michael Ju Hyeok Lee, Douglas Ele Martin, Harsh Dev Sharma
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Patent number: D804494Type: GrantFiled: May 24, 2016Date of Patent: December 5, 2017Assignee: SAP SEInventors: Jens Bombolowsky, Dev Sharma, Sabine Finke
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Patent number: D808408Type: GrantFiled: May 24, 2016Date of Patent: January 23, 2018Assignee: SAP SEInventors: Jens Bombolowsky, Dev Sharma