Patents by Inventor Dev Sharma

Dev Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6674587
    Abstract: The present invention relates to a method of deposition of an absorbing material upon a plastic/glass substrate by vacuum coating at an angle of inclination between 5° to 30° and using a mask on the evaporation source to produce a graded film material and a method for the preparation of graded density absorbing film useful as an antiglare optical device for protecting the eyes by reducing the glare by absorbing the light intensity falling upon it in a non-uniform fashion.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: January 6, 2004
    Assignee: Council of Scientific Research
    Inventors: Deep Singh Chhabra, Parinam Krisna Rao, Bipin Dev Sharma, Dharambir Singh Dodd, Virender Singh, Sanjay Sharma
  • Publication number: 20030016460
    Abstract: The present invention relates to a method of deposition of an absorbing material upon a plastic/glass substrate by vacuum coating at an angle of inclination between 5° to 30° and using a mask on the evaporation source to produce a graded film material and a method for the preparation of graded density absorbing film useful as an antiglare optical device for protecting the eyes by reducing the glare by absorbing the light intensity falling upon it in a non-uniform fashion.
    Type: Application
    Filed: March 30, 2001
    Publication date: January 23, 2003
    Inventors: Deep Singh Chhabra, Parinam Krisna Rao, Bipin Dev Sharma, Dharambir Singh Dodd, Virender Singh, Sanjay Sharma
  • Patent number: 6208907
    Abstract: A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Visweswara Rao Kodali, Douglas Ele Martin, Harsh Dev Sharma
  • Patent number: 6107852
    Abstract: A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: August 22, 2000
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Michael Ju Hyeok Lee, Visweswara Rao Kodali, Harsh Dev Sharma
  • Patent number: 6037804
    Abstract: A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: March 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: Christopher McCall Durham, Visweswara Rao Kodali, Michael Ju Hyeok Lee, Douglas Ele Martin, Harsh Dev Sharma