Patents by Inventor Devendra Natekar

Devendra Natekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8518750
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, David Chau, Gregory M. Chrysler, Devendra Natekar
  • Publication number: 20130122656
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Application
    Filed: January 4, 2013
    Publication date: May 16, 2013
    Inventors: Yoshihiro Tomita, David Chau, Gregory M. Chrysler, Devendra Natekar
  • Patent number: 8409924
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 2, 2013
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, David Chau, Gregory M Chrysler, Devendra Natekar
  • Publication number: 20120289002
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Application
    Filed: July 23, 2012
    Publication date: November 15, 2012
    Applicant: Intel Corporation
    Inventors: Yoshihiro Tomita, David Chau, Gregory M. Chrysler, Devendra Natekar
  • Patent number: 8227907
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, David Chau, Gregory M. Chrysler, Devendra Natekar
  • Publication number: 20110103438
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Application
    Filed: January 11, 2011
    Publication date: May 5, 2011
    Applicant: INTEL CORPORATION
    Inventors: Yoshihiro Tomita, David Chau, Gregory M. Chrysler, Devendra Natekar
  • Patent number: 7915081
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, David Chau, Gregory M. Chrysler, Devendra Natekar
  • Publication number: 20100193952
    Abstract: A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.
    Type: Application
    Filed: April 14, 2009
    Publication date: August 5, 2010
    Inventors: Leonel Arana, Michael Newman, Devendra Natekar
  • Patent number: 7592704
    Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: September 22, 2009
    Assignee: Intel Corporation
    Inventors: Terry L. Sterrett, Devendra Natekar
  • Patent number: 7589424
    Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: September 15, 2009
    Assignee: Intel Corporation
    Inventors: Sriram Muthukumar, Devendra Natekar
  • Patent number: 7528006
    Abstract: A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 5, 2009
    Assignee: Intel Corporation
    Inventors: Leonel Arana, Michael Newman, Devendra Natekar
  • Patent number: 7514116
    Abstract: Horizontal carbon nanotubes may be used for on-die routing and other applications. In one example, a catalyst is applied to a plurality of different points on a substrate. Carbon nanotubes are then grown vertically on the plurality of different points to form a plurality of vertical carbon nanotube structures on the substrate. The vertical carbon nanotuhe structures are then rolled to form horizontal carbon nanotube structures.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Devendra Natekar, Yoshihiro Tomita, Chi-Won Hwang
  • Publication number: 20090072013
    Abstract: Nano-scale particle paste may be used for on-die routing and other applications using deposition and inkjet printing. A metal paste is applied to a surface of a die to electrically couple two spaced apart connection points of the die. Alternatively, or in addition, the paste may contain carbon nanotubes. The paste may be used on other surfaces as well.
    Type: Application
    Filed: November 25, 2008
    Publication date: March 19, 2009
    Inventors: DEVENDRA NATEKAR, Yoshihiro Tomita, Chi-Won Hwang
  • Publication number: 20080303159
    Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
    Type: Application
    Filed: August 8, 2008
    Publication date: December 11, 2008
    Inventors: Sriram Muthukumar, Devendra Natekar
  • Publication number: 20080265391
    Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.
    Type: Application
    Filed: July 8, 2008
    Publication date: October 30, 2008
    Inventors: Terry L. STERRETT, Devendra NATEKAR
  • Patent number: 7443030
    Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Sriram Muthukumar, Devendra Natekar
  • Publication number: 20080251932
    Abstract: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 16, 2008
    Inventors: Leonel R. Arana, Devendra Natekar, Michael Newman, Charan K. Gurumurthy
  • Patent number: 7413995
    Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Terry L. Sterrett, Devendra Natekar
  • Patent number: 7402515
    Abstract: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Leonel R. Arana, Devendra Natekar, Michael Newman, Charan K. Gurumurthy
  • Publication number: 20070231953
    Abstract: An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 4, 2007
    Inventors: Yoshihiro Tomita, David Chau, Gregory M. Chrysler, Devendra Natekar