Patents by Inventor Devendra Natekar

Devendra Natekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070152194
    Abstract: Nano-scale particle paste may be used for on-die routing and other applications using deposition and ink-jet printing. A metal paste is applied to a surface of a die to electrically couple two spaced apart connection points of the die. Alternatively, or in addition, the paste may contain carbon nanotubes. The paste may be used on other surfaces as well.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Devendra Natekar, Yoshihiro Tomita, Chi-Won Hwang
  • Publication number: 20070090517
    Abstract: Disclosed are embodiments of a stacked die package including a thermally conductive block disposed in the substrate. The die stack may include a lower die thermally coupled with the conductive block and one or more upper die disposed on the lower die. The upper die may be electrically interconnected to one another and with the lower die by a number of thru-vias, and the die stack may also be electrically coupled with the substrate. Other embodiments are described and claimed.
    Type: Application
    Filed: October 5, 2005
    Publication date: April 26, 2007
    Inventors: Sung-won Moon, Devendra Natekar, Chia-pin Chiu
  • Publication number: 20070000592
    Abstract: An assembly arrangement includes an assembly head having plural nozzles. The assembly head is designed to operate on a group of attach sites of a substrate at substantially the same time and is designed to be moveable relative to the substrate to allow the plural nozzles to successively operate on different groups of attach sites of the substrate.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Farokh Fares, Erming Luo, Devendra Natekar
  • Publication number: 20070001266
    Abstract: A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Leonel Arana, Michael Newman, Devendra Natekar
  • Publication number: 20060290002
    Abstract: A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2005
    Publication date: December 28, 2006
    Inventors: Leonel Arana, Devendra Natekar, Michael Newman, Charan Gurumurthy
  • Patent number: 7144299
    Abstract: Electronic device support and processing methods are described. One embodiment includes a method of processing an electronic device including solder bumps extending therefrom. The method includes providing at least one fluid selected from the group consisting of electrorheological fluids and magnorheological fluids on a support structure. The solder bumps extending from the electronic device are positioned in the fluid. The fluid is activated by applying a field selected from the group consisting of an electric field and a magnetic field to the fluid. The activated fluid mechanically holds the electronic device in place. A surface of the electronic device is polished while the electronic device is held in place by the activated fluid. The fluid is deactivated by removing the applied field from the fluid, and the electronic device is separated from the deactivated fluid. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: December 5, 2006
    Assignee: Intel Corporation
    Inventors: Leonel R. Arana, Terry L. Sterrett, Devendra Natekar
  • Publication number: 20060252354
    Abstract: Electronic device support and processing methods are described. One embodiment includes a method of processing an electronic device including solder bumps extending therefrom. The method includes providing at least one fluid selected from the group consisting of electrorheological fluids and magnorheological fluids on a support structure. The solder bumps extending from the electronic device are positioned in the fluid. The fluid is activated by applying a field selected from the group consisting of an electric field and a magnetic field to the fluid. The activated fluid mechanically holds the electronic device in place. A surface of the electronic device is polished while the electronic device is held in place by the activated fluid. The fluid is deactivated by removing the applied field from the fluid, and the electronic device is separated from the deactivated fluid. Other embodiments are described and claimed.
    Type: Application
    Filed: May 9, 2005
    Publication date: November 9, 2006
    Inventors: Leonel Arana, Terry Sterrett, Devendra Natekar
  • Publication number: 20060189121
    Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
    Type: Application
    Filed: March 23, 2006
    Publication date: August 24, 2006
    Inventors: Sriram Muthukumar, Devendra Natekar
  • Patent number: 7049208
    Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
    Type: Grant
    Filed: October 11, 2004
    Date of Patent: May 23, 2006
    Assignee: Intel Corporation
    Inventors: Sriram Muthukumar, Devendra Natekar
  • Publication number: 20060079079
    Abstract: Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.
    Type: Application
    Filed: October 11, 2004
    Publication date: April 13, 2006
    Inventors: Sriram Muthukumar, Devendra Natekar
  • Publication number: 20060046433
    Abstract: Wafer thinning may be accomplished by grinding while the wafer is held in the fixture. The fixture may have a series of protrusions that form an interference fit with surface features extending outwardly from the non-thinned surface of the wafer to be thinned. In some embodiments, a releasable adhesive may be utilized to augment the interference effect. Also, in some embodiments, openings in a shape memory material may be utilized that, upon heating, more firmly engage the bumps on the wafer to be thinned.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Terry Sterrett, Leonel Arana, Devendra Natekar
  • Publication number: 20060038303
    Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 23, 2006
    Inventors: Terry Sterrett, Devendra Natekar
  • Patent number: 6803653
    Abstract: A semiconductor structure includes a substrate and a semiconductor devices secured to the substrate. A stabilizing member is secured to the semiconductor device, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the substrate. The bending stiffness of the substrate is substantially the same as the bending stiffness of the stabilizing member, wherein: bending stiffness=Et3, with E=Young's modulus, and t=thickness. In another embodiment, a stabilizing member is secured to the substrate, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the die. The bending stiffness of the die is substantially the same as the bending stiffness of the stabilizing member, with bending stiffness defined as above.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: October 12, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert E. Likins, Richard C. Blish, II, Sharad M. Shah, Sidharth Sidharth, Devendra Natekar