Patents by Inventor Dharmendra S. Modha

Dharmendra S. Modha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LENS DISTORTION CORRECTION USING A NEUROSYNAPTIC CIRCUIT
    Publication number: 20180253825
    Abstract: One or more embodiments provide a neurosynaptic circuit that includes multiple neurosynaptic core circuits that: perform image distortion correction by converting a source image to a destination image by: taking as input a sequence of image frames of a video with one or more channels per frame, and converting dimensions and pixel distortion coefficients of each frame as one or more corresponding neuronal firing events. Each distorted pixel is mapped to zero or more undistorted pixels by processing each neuronal firing event corresponding to each pixel of each image frame. Corresponding pixel intensity values of each distorted pixel are processed to output undistorted pixels for each image frame as neuronal firing events for a spike representation of the destination image.
    Type: Application
    Filed: April 30, 2018
    Publication date: September 6, 2018
    Inventors: Alexander Andreopoulos, Daniel F. Gruhl, Michael Karasick, Dharmendra S. Modha
  • LENS DISTORTION CORRECTION USING A NEUROSYNAPTIC CIRCUIT
    Publication number: 20180253833
    Abstract: One or more embodiments provide method for image distortion correction including receiving, by multiple neurosynaptic core circuits, a set of inputs comprising image dimensions and pixel distortion coefficients for at least one image frame via at least one input core circuit. Each distorted pixel is mapped to zero or more undistorted pixels by processing the set of inputs corresponding to each pixel of the at least one image frame by the at least one input core circuit. Corresponding pixel intensity values of each distorted pixel are routed to output undistorted pixels for each image frame via the at least one output core circuit.
    Type: Application
    Filed: April 30, 2018
    Publication date: September 6, 2018
    Inventors: Alexander Andreopoulos, Daniel F. Gruhl, Michael Karasick, Dharmendra S. Modha
  • DUAL DETERMINISTIC AND STOCHASTIC NEUROSYNAPTIC CORE CIRCUIT
    Publication number: 20180232634
    Abstract: One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated.
    Type: Application
    Filed: April 10, 2018
    Publication date: August 16, 2018
    Inventors: Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • LONG-SHORT TERM MEMORY (LSTM) CELLS ON SPIKING NEUROMORPHIC HARDWARE
    Publication number: 20180232631
    Abstract: Long-short term memory (LSTM) cells on spiking neuromorphic hardware are provided. In various embodiments, such systems comprise a spiking neurosynaptic core. The neurosynaptic core comprises a memory cell, an input gate operatively coupled to the memory cell and adapted to selectively admit an input to the memory cell, and an output gate operatively coupled to the memory cell an adapted to selectively release an output from the memory cell. The memory cell is adapted to maintain a value in the absence of input.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 16, 2018
    Inventors: Rathinakumar Appuswamy, Michael Beyeler, Pallab Datta, Myron Flickner, Dharmendra S. Modha
  • Lens distortion correction using a neurosynaptic system
    Patent number: 10043248
    Abstract: One or more embodiments provide a system and circuit for image distortion correction. The system includes neurosynaptic core circuits that: receive a set of inputs comprising image dimensions and pixel distortion coefficients for at least one image frame via at least one input core circuit, map each distorted pixel to zero or more undistorted pixels by processing the set of inputs corresponding to each pixel of the at least one image frame by the at least one input core circuit, and route corresponding pixel intensity values of each distorted pixel to output undistorted pixels for each image frame via at least one output core circuit.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Andreopoulos, Daniel F. Gruhl, Michael Karasick, Dharmendra S. Modha
  • Lens distortion correction using a neurosynaptic circuit
    Patent number: 10043241
    Abstract: One or more embodiments provide a neurosynaptic circuit that includes multiple neurosynaptic core circuits that: perform image sharpening by converting a source image to a sharpened destination image by: taking as input a sequence of image frames of a video with one or more channels per frame, and representing the intensity of each pixel of each channel of each frame as neural spikes, and processing neural spike representations of the sharpened destination image for outputting a spike representation of the sharpened destination image.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Andreopoulos, Daniel F. Gruhl, Michael Karasick, Dharmendra S. Modha
  • Scene understanding using a neurosynaptic system
    Patent number: 10043110
    Abstract: Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Steven K. Esser, Dharmendra S. Modha
  • COMPOSITIONAL PROTOTYPES FOR SCALABLE NEUROSYNAPTIC NETWORKS
    Publication number: 20180211161
    Abstract: Embodiments of the invention provide a method comprising maintaining a library of one or more compositional prototypes. Each compositional prototype is associated with a neurosynaptic program. The method further comprises searching the library based on one or more search parameters. At least one compositional prototype satisfying the search parameters is selected. A neurosynaptic network is generated or extended by applying one or more rules associated with the selected compositional prototypes.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 26, 2018
    Inventors: Arnon Amir, Pallab Datta, Dharmendra S. Modha, Benjamin G. Shaw
  • PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE ARRAY LAYOUT
    Publication number: 20180211163
    Abstract: Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 26, 2018
    Inventors: John V. Arthur, John E. Barth, JR., Paul A. Merolla, Dharmendra S. Modha
  • AREA-EFFICIENT, RECONFIGURABLE, ENERGY-EFFICIENT, SPEED-EFFICIENT NEURAL NETWORK SUBSTRATE
    Publication number: 20180197075
    Abstract: Architectures for multicore neuromorphic systems are provided. In various embodiments, a neural network description is read. The neural network description describes a plurality of logical cores. A plurality of precedence relationships are determined among the plurality of logical cores. Based on the plurality of precedence relationships, a schedule is generated that assigns the plurality of logical cores to a plurality of physical cores at a plurality of time slices. Based on the schedule, the plurality of logical cores of the neural network description are executed on the plurality of physical cores.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 12, 2018
    Inventor: Dharmendra S. Modha
  • PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES
    Publication number: 20180197073
    Abstract: One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Daniel J. Friedman, Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno
  • PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES
    Publication number: 20180197074
    Abstract: One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Daniel J. Friedman, Seongwon Kim, Chung H. Lam, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno
  • Transform for a neurosynaptic core circuit
    Patent number: 10019667
    Abstract: Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Rathinakumar Appuswamy, Myron D. Flickner, Dharmendra S. Modha
  • Unsupervised, supervised and reinforced learning via spiking computation
    Patent number: 10019669
    Abstract: The present invention relates to unsupervised, supervised and reinforced learning via spiking computation. The neural network comprises a plurality of neural modules. Each neural module comprises multiple digital neurons such that each neuron in a neural module has a corresponding neuron in another neural module. An interconnection network comprising a plurality of edges interconnects the plurality of neural modules. Each edge interconnects a first neural module to a second neural module, and each edge comprises a weighted synaptic connection between every neuron in the first neural module and a corresponding neuron in the second neural module.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventor: Dharmendra S. Modha
  • STRUCTURAL DESCRIPTIONS FOR NEUROSYNAPTIC NETWORKS
    Publication number: 20180189644
    Abstract: Embodiments of the invention provide a method comprising creating a structural description for at least one neurosynaptic core circuit. Each core circuit comprises an interconnect network including plural electronic synapses for interconnecting one or more electronic neurons with one or more electronic axons. The structural description defines a desired neuronal activity for the core circuits. The desired neuronal activity is simulated by programming the core circuits with the structural description. The structural description controls routing of neuronal firing events for the core circuits.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Inventor: Dharmendra S. Modha
  • INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES OF A PROCESSOR ARRAY
    Publication number: 20180189233
    Abstract: Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.
    Type: Application
    Filed: February 26, 2018
    Publication date: July 5, 2018
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arhur, John E. Barth, JR., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • IMPLEMENTING A NEURAL NETWORK ALGORITHM ON A NEUROSYNAPTIC SUBSTRATE BASED ON METADATA ASSOCIATED WITH THE NEURAL NETWORK ALGORITHM
    Publication number: 20180189637
    Abstract: One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a metadata analysis unit for analyzing metadata information associated with one or more portions of an adjacency matrix representation of the neural network, and a mapping unit for mapping the one or more portions of the matrix representation onto the neurosynaptic substrate based on the metadata information.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Inventors: Arnon Amir, Rathinakumar Appuswamy, Pallab Datta, Myron D. Flickner, Paul A. Merolla, Dharmendra S. Modha, Benjamin G. Shaw
  • Yield tolerance in a neurosynaptic system
    Patent number: 9992057
    Abstract: Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Dual deterministic and stochastic neurosynaptic core circuit
    Patent number: 9984324
    Abstract: One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Compositional prototypes for scalable neurosynaptic networks
    Patent number: 9984323
    Abstract: Embodiments of the invention provide a method comprising maintaining a library of one or more compositional prototypes. Each compositional prototype is associated with a neurosynaptic program. The method further comprises searching the library based on one or more search parameters. At least one compositional prototype satisfying the search parameters is selected. A neurosynaptic network is generated or extended by applying one or more rules associated with the selected compositional prototypes.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Arnon Amir, Pallab Datta, Dharmendra S. Modha, Benjamin G. Shaw