Patents by Inventor Dhiraj Kumar

Dhiraj Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060268913
    Abstract: A system for streaming incoming data packets into a buffer memory is presented. The system may receive incoming data packets over a variety of interfaces and separate the data packet into a header page and one or more data page. The system may interface with a header processor and send header pages to the header processor to be modified. Data pages from the incoming data packets are streamed to a central staging memory, allowing the use of a simple first-in-first-out (FIFO) buffer. The system may receive modified headers from the header processor and provide multiple copies of data packets for multicast or sampling purposes. Data packet copies may then be written to an external memory buffer over one or more external memory channels. The system may also provide an error recovery process to account for corrupt data packets streamed to the external memory buffer.
    Type: Application
    Filed: May 27, 2005
    Publication date: November 30, 2006
    Applicant: UTStarcom, Inc.
    Inventors: Kanwar Singh, Dhiraj Kumar
  • Patent number: 5974255
    Abstract: An object oriented test provides a hierarchy of classes under test, each of the classes under test having a predefined inheritance structure. The test provides a test class for each corresponding class under test. Each class under test has a test member function, a set state member function, a verify state member function, and a test vector which includes an initial complete state, an expected complete state, a set of function inputs for a member function being tested, and a set of expected results. The test sets an initial complete state of the test class by implicitly calling the set state member functions through the inheritance structure of the test classes. Next a member function of a desired class under test is executed. The final complete state of the class under test as well as the outputs and returned values of all member functions which were executed are compared with the set of expected results.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: October 26, 1999
    Assignee: Motorola, Inc.
    Inventors: Dhiraj Kumar Gossain, Dana Mark Rigg
  • Patent number: 5678040
    Abstract: A hierarchical design transaction method which provides a shared project workspace and an individual user workspace. A desired portion of a hierarchical design is checked out from the shared project workspace and is edited in the individual user workspace. A new version of the desired portion of the hierarchical design is checked into the shared project workspace. Concurrently, another individual user workspace is provided, and another desired portion of the hierarchical design is checked out, edited and checked in. These steps are repeated for each of a plurality of desired portions of the hierarchical design, to continuously guarantee consistency between the shared project workspace and each individual user workspace.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: October 14, 1997
    Assignee: Motorola, Inc.
    Inventors: Venu Vasudevan, Dhiraj Kumar Gossain, Dana Mark Rigg, Don Michael Gibson, Tron Kyle Womack