Patents by Inventor Dhrumil Gandhi
Dhrumil Gandhi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180196909Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: ApplicationFiled: March 6, 2018Publication date: July 12, 2018Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 9910950Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: GrantFiled: August 22, 2016Date of Patent: March 6, 2018Assignee: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Publication number: 20170104004Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 9530795Abstract: A semiconductor device includes a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.Type: GrantFiled: February 23, 2016Date of Patent: December 27, 2016Assignee: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Publication number: 20160357897Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 9424387Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: GrantFiled: January 26, 2015Date of Patent: August 23, 2016Assignee: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Publication number: 20160172375Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.Type: ApplicationFiled: February 23, 2016Publication date: June 16, 2016Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 9269702Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.Type: GrantFiled: February 21, 2014Date of Patent: February 23, 2016Assignee: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Publication number: 20150143321Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: ApplicationFiled: January 26, 2015Publication date: May 21, 2015Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 9009641Abstract: A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.Type: GrantFiled: January 12, 2013Date of Patent: April 14, 2015Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt, Daryl Fox
-
Patent number: 8966424Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: GrantFiled: September 27, 2013Date of Patent: February 24, 2015Assignee: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 8863063Abstract: A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned.Type: GrantFiled: March 15, 2013Date of Patent: October 14, 2014Assignee: Tela Innovations, Inc.Inventors: Scott T. Becker, Michael C. Smayling, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt, Daryl Fox
-
Publication number: 20140167117Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.Type: ApplicationFiled: February 21, 2014Publication date: June 19, 2014Applicant: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 8661392Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.Type: GrantFiled: October 13, 2010Date of Patent: February 25, 2014Assignee: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Publication number: 20140035152Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: ApplicationFiled: September 27, 2013Publication date: February 6, 2014Applicant: TELA INNOVATIONS, INC.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 8549455Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: GrantFiled: July 2, 2012Date of Patent: October 1, 2013Assignee: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Publication number: 20130207199Abstract: A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned.Type: ApplicationFiled: March 15, 2013Publication date: August 15, 2013Inventors: Scott T. Becker, Michael C. Smayling, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt, Daryl Fox
-
Publication number: 20130126978Abstract: A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.Type: ApplicationFiled: January 12, 2013Publication date: May 23, 2013Inventors: Scott T. Becker, Michael C. Smayling, Dhrumil Gandhi, Jim Mali, Carole Lambert, Jonathan R. Quandt, Daryl Fox
-
Publication number: 20120273841Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: ApplicationFiled: July 2, 2012Publication date: November 1, 2012Applicant: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi
-
Patent number: 8214778Abstract: A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.Type: GrantFiled: July 2, 2009Date of Patent: July 3, 2012Assignee: Tela Innovations, Inc.Inventors: Jonathan R. Quandt, Scott T. Becker, Dhrumil Gandhi