Patents by Inventor Di Li

Di Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8716075
    Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette, Chandra Mouli, Howard Kirsch, Di Li
  • Publication number: 20140115450
    Abstract: This application provides a method and system of evidence preservation for digital documents. The method comprises: converting, by a client, the digital document to a document code, which is uniquely corresponding to the digital document; uploading, from the client, the document code and first attribute information of the client to a server, wherein the first attribute information includes user information and geographical position information of the client; and incorporating, by the server, second attribute information into the document code and the first attribute information to form a code file, and preserving the code file in a code file database of the server, wherein the second attribute information includes time information indicating when the document code is received by the server; wherein when contents of the digital document are changed, contents of the document code are changed accordingly.
    Type: Application
    Filed: December 23, 2011
    Publication date: April 24, 2014
    Applicant: DOMINATOR IP CO., LTD.
    Inventors: Shan Zhong, Yaou Li, Di Li, Dalong Shi, Peng Wang, HuiChung Che, Hsiangshuai Wu
  • Patent number: 8686487
    Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Chandra Mouli, Di Li
  • Publication number: 20140051214
    Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.
    Type: Application
    Filed: February 7, 2013
    Publication date: February 20, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jun Liu, Michael P. Violette, Chandra Mouli, Howard Kirsch, Di Li
  • Publication number: 20140035021
    Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
    Type: Application
    Filed: October 8, 2013
    Publication date: February 6, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
  • Publication number: 20140031722
    Abstract: A pelvic digitizer device comprises a body comprising: a shaft having a tooling end and a handle end with a handle for being manipulated. A visual guide is oriented in a reference plane of the digitizer device. A cup is connected to the tooling end and adapted to be received in an acetabulum of a patient. An inertial sensor unit is connected to the body, the inertial sensor unit having a preset orientation aligned with the reference plane.
    Type: Application
    Filed: July 30, 2013
    Publication date: January 30, 2014
    Applicant: ORTHOSOFT, INC.
    Inventors: Di Li, Louis-Philippe Amiot, Don Dye, Myriam Valin, Isabelle Robitaille, Francois Paradis, Karine Duval, Yonik Breton, Simon Ferron-Forget
  • Publication number: 20140001534
    Abstract: A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Inventors: Shenqing FANG, Tung-Sheng CHEN, Tim THURGATE, Di LI
  • Publication number: 20130313437
    Abstract: The present invention relates to a positron tomography imaging apparatus for a multiphase flow in an oil pipeline, which apparatus utilizes positron and electron annihilation generating a pair of coincidence gamma-rays of 511 keV energy as tomography imaging means and provides an on-line tomography imaging function for metering a multiphase flow in an oil pipeline of an oil field. The apparatus comprises a plurality of sets of parallel high-precision gamma-ray detector arrays with a particular space structure arrangement, a positron radioactive source and a shield, and can acquire a phase fraction of such multiphase flow mixture as oil, gas and water under a condition of a single radioactive source by combining an image processing function. The design of a plurality of sets of high-precision detector arrays also greatly improves accuracy of a multiphase flow metering and its applicability in multiphase flows of different flow patterns.
    Type: Application
    Filed: January 20, 2011
    Publication date: November 28, 2013
    Applicants: LANZHOU HAIMO TECHNOLOGIES CO., LTD.
    Inventors: Hong Di Li, Jige Chen
  • Patent number: 8580645
    Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
  • Patent number: 8545803
    Abstract: Modified molecular sieve characterized by improved sodium-resisting contamination activity and preparation method thereof are provided. The method comprises: adding molecular sieve in phosphorus-containing organic solution, and reacting for 10-200 minutes at temperature of 70-200° C. and pressure of 0.2-1.2 MPa, and then filtering, drying and calcining. The said modified molecular sieve contains 90-99 wt. % molecular sieve as dry basis and 1-10 wt. % phosphorus as oxide. The said method can improve the capability of sodium-resisting contamination effectively, and its technology is simple and fits the existing catalyst production apparatus and process. The said modified molecular sieve has high sodium-resisting contamination activity, and the model catalyst by sodium contamination has high activity retention.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: October 1, 2013
    Assignee: PetroChina Company Limited
    Inventors: Xionghou Gao, Dong Ji, Haitao Zhang, Hongchang Duan, Di Li, ZhengGuo Tan, Yi Su, Chenxi Zhang, Yi Wang, Yanqing Ma, Yanbo Sun
  • Patent number: 8415223
    Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: April 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
  • Patent number: 8395214
    Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: March 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Di Li, Michael P. Violette, Chandra Mouli, Howard Kirsch
  • Publication number: 20120275227
    Abstract: A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 1, 2012
    Inventors: Seiichi ARITOME, Haitao Liu, Di Li
  • Publication number: 20120275994
    Abstract: A method for producing double-component modified molecular sieve comprises adding molecular sieve to an aqueous solution containing phosphorus to form a mixture, allowing the mixture to react at pH of 1-10, temperature of 70-200° C. and pressure of 0.2-1.2 MPa for 10-200 min, and then filtering, drying and baking the resultant to obtain phosphorus-modified molecular sieve, and then adding the phosphorus-modified molecular sieve to an aqueous solution containing silver ions, allowing the phosphorus-modified molecular sieve to react with silver ions at 0-100° C. in dark condition for 30-150 min, and then filtering, drying and baking. The obtained double-component modified molecular sieve contains 88-99 wt % molecular sieve with a ratio of silica to alumina between 15 and 60, 0.5-10 wt % phosphorus (based on oxides) and 0.01-2 wt % silver (based on oxides), all based on dry matter. A catalyst produced from the double-component modified molecular sieve has improved hydrothermal stability and microactivity.
    Type: Application
    Filed: December 1, 2009
    Publication date: November 1, 2012
    Applicant: PetroChina Company Limited
    Inventors: Xionghou Gao, Dong Ji, Haitao Zhang, Hongchang Duan, Di Li, ZhengGuo Tan, Yi Su, Zhicheng Tang, Yi Wang, Yanqing Ma, Yanbo Sun
  • Publication number: 20120213695
    Abstract: Modified molecular sieve characterized by improved sodium-resisting contamination activity and preparation method thereof are provided. The method comprises: adding molecular sieve in phosphorus-containing organic solution, and reacting for 10-200 minutes at temperature of 70-200° C. and pressure of 0.2-1.2 MPa, and then filtering, drying and calcining. The said modified molecular sieve contains 90-99 wt. % molecular sieve as dry basis and 1-10 wt. % phosphorus as oxide. The said method can improve the capability of sodium-resisting contamination effectively, and its technology is simple and fits the existing catalyst production apparatus and process. The said modified molecular sieve has high sodium-resisting contamination activity, and the model catalyst by sodium contamination has high activity retention.
    Type: Application
    Filed: December 1, 2009
    Publication date: August 23, 2012
    Applicant: PetroChina Company Limited
    Inventors: Xionghou Gao, Dong Ji, Haitao Zhang, Hongchang Duan, Di Li, ZhengGuo Tan, Yi Su, Chenxi Zhang, Yi Wang, Yanqing Ma, Yanbo Sun
  • Patent number: 8223549
    Abstract: A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: July 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Seiichi Aritome, Haitao Liu, Di Li
  • Publication number: 20120132979
    Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
    Type: Application
    Filed: February 3, 2012
    Publication date: May 31, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kirk Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen
  • Publication number: 20120083489
    Abstract: The invention provides novel bis-pyridylpyridones which are antagonists at the melanin-concentrating hormone receptor 1 (MCHR1), pharmaceutical compositions containing them, processes for their preparation, and their use in therapy and for the treatment of obesity and diabetes.
    Type: Application
    Filed: June 2, 2010
    Publication date: April 5, 2012
    Inventors: Siegfried Benjamin Christensen IV, Donghui Qin, Shenglin Chen, Xing Huang, Di Li, Fei Li, Lei Li, Xiaojuan Lin, Shi Lu, Zhen Lu, Maoyun Lv, Chuanning Wang, Chengde Wu, Mei Xiao, Haiyu Yu, Weina Zhang, Zhiliu Zhang
  • Publication number: 20120077794
    Abstract: The invention provides novel bis-pyridylpyridones which are antagonists at the melanin-concentrating hormone receptor 1 (MCHR1), pharmaceutical compositions containing them, processes for their preparation, and their use in therapy and for the treatment of obesity and diabetes.
    Type: Application
    Filed: June 2, 2010
    Publication date: March 29, 2012
    Applicant: GLAXSMITHKLINE LLC
    Inventors: Siegfried Benjamin Christensen, IV, Donghui Qin, Shenglin Chen, Xing Huang, Di Li, Fei Li, Xiaojuan Lin, Shi Lu, Maoyun Lv, Chengde Wu, Weiliang Xu, Gang Yan, Jianxing Yuan, Weina Zhang, Zhiliu Zhang
  • Patent number: 8129781
    Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: March 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D Prall, Behnam Moradi, Seiichi Aritome, Di Li, Chris Larsen