Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract: This application provides a method and system of evidence preservation for digital documents. The method comprises: converting, by a client, the digital document to a document code, which is uniquely corresponding to the digital document; uploading, from the client, the document code and first attribute information of the client to a server, wherein the first attribute information includes user information and geographical position information of the client; and incorporating, by the server, second attribute information into the document code and the first attribute information to form a code file, and preserving the code file in a code file database of the server, wherein the second attribute information includes time information indicating when the document code is received by the server; wherein when contents of the digital document are changed, contents of the document code are changed accordingly.

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: A pelvic digitizer device comprises a body comprising: a shaft having a tooling end and a handle end with a handle for being manipulated. A visual guide is oriented in a reference plane of the digitizer device. A cup is connected to the tooling end and adapted to be received in an acetabulum of a patient. An inertial sensor unit is connected to the body, the inertial sensor unit having a preset orientation aligned with the reference plane.

Abstract: A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.

Abstract: The present invention relates to a positron tomography imaging apparatus for a multiphase flow in an oil pipeline, which apparatus utilizes positron and electron annihilation generating a pair of coincidence gamma-rays of 511 keV energy as tomography imaging means and provides an on-line tomography imaging function for metering a multiphase flow in an oil pipeline of an oil field. The apparatus comprises a plurality of sets of parallel high-precision gamma-ray detector arrays with a particular space structure arrangement, a positron radioactive source and a shield, and can acquire a phase fraction of such multiphase flow mixture as oil, gas and water under a condition of a single radioactive source by combining an image processing function. The design of a plurality of sets of high-precision detector arrays also greatly improves accuracy of a multiphase flow metering and its applicability in multiphase flows of different flow patterns.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: Modified molecular sieve characterized by improved sodium-resisting contamination activity and preparation method thereof are provided. The method comprises: adding molecular sieve in phosphorus-containing organic solution, and reacting for 10-200 minutes at temperature of 70-200° C. and pressure of 0.2-1.2 MPa, and then filtering, drying and calcining. The said modified molecular sieve contains 90-99 wt. % molecular sieve as dry basis and 1-10 wt. % phosphorus as oxide. The said method can improve the capability of sodium-resisting contamination effectively, and its technology is simple and fits the existing catalyst production apparatus and process. The said modified molecular sieve has high sodium-resisting contamination activity, and the model catalyst by sodium contamination has high activity retention.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract: A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.

Abstract: A method for producing double-component modified molecular sieve comprises adding molecular sieve to an aqueous solution containing phosphorus to form a mixture, allowing the mixture to react at pH of 1-10, temperature of 70-200° C. and pressure of 0.2-1.2 MPa for 10-200 min, and then filtering, drying and baking the resultant to obtain phosphorus-modified molecular sieve, and then adding the phosphorus-modified molecular sieve to an aqueous solution containing silver ions, allowing the phosphorus-modified molecular sieve to react with silver ions at 0-100° C. in dark condition for 30-150 min, and then filtering, drying and baking. The obtained double-component modified molecular sieve contains 88-99 wt % molecular sieve with a ratio of silica to alumina between 15 and 60, 0.5-10 wt % phosphorus (based on oxides) and 0.01-2 wt % silver (based on oxides), all based on dry matter. A catalyst produced from the double-component modified molecular sieve has improved hydrothermal stability and microactivity.

Abstract: Modified molecular sieve characterized by improved sodium-resisting contamination activity and preparation method thereof are provided. The method comprises: adding molecular sieve in phosphorus-containing organic solution, and reacting for 10-200 minutes at temperature of 70-200° C. and pressure of 0.2-1.2 MPa, and then filtering, drying and calcining. The said modified molecular sieve contains 90-99 wt. % molecular sieve as dry basis and 1-10 wt. % phosphorus as oxide. The said method can improve the capability of sodium-resisting contamination effectively, and its technology is simple and fits the existing catalyst production apparatus and process. The said modified molecular sieve has high sodium-resisting contamination activity, and the model catalyst by sodium contamination has high activity retention.

Abstract: A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: The invention provides novel bis-pyridylpyridones which are antagonists at the melanin-concentrating hormone receptor 1 (MCHR1), pharmaceutical compositions containing them, processes for their preparation, and their use in therapy and for the treatment of obesity and diabetes.

Abstract: The invention provides novel bis-pyridylpyridones which are antagonists at the melanin-concentrating hormone receptor 1 (MCHR1), pharmaceutical compositions containing them, processes for their preparation, and their use in therapy and for the treatment of obesity and diabetes.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.