Abstract: In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into the semiconductor substrate and extend partially under the sidewalls to allow the operation of the floating gates with respect to the buried bit line which act as drains and sources. A control gate is deposited over a row of sidewalls orthogonal to the bit lines and extending the length of a flash memory word line. The polysilicon sidewall split gate flash memory cells are programmed, read and erased by a combination of voltages applied to the control gate and the bit lines partially underlying the sidewalls.

Abstract: A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate.

Abstract: A split gate EEPROM memory device formed on a doped silicon semi-conductor substrate starting with an initial oxide layer with an undoped first polysilicon layer formed thereon. A polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.

Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage.

Abstract: Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.

Abstract: A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thick floating gate layer of doped polysilicon over the tunnel oxide layer filling the trenches and extending above the trenches. Etch the floating gate layer down below the top of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thick control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes.

Abstract: Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.

Abstract: A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

Abstract: Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.

Abstract: A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.

Abstract: An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack.

Abstract: In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into the semiconductor substrate and extend partially under the sidewalls to allow the operation of the floating gates with respect to the buried bit line which act as drains and sources. A control gate is deposited over a row of sidewalls orthogonal to the bit lines and extending the length of a flash memory word line. The polysilicon sidewall split gate flash memory cells are programmed, read and erased by a combination of voltages applied to the control gate and the bit lines partially underlying the sidewalls.

Abstract: A split gate electrode MOS FET device includes a tunnel oxide layer formed over a semiconductor substrate. Over the tunnel oxide layer, a doped first polysilicon layer is formed with a top surface. A native oxide which forms over the doped first polysilicon layer may have been removed as an option. On the top surface of the first polysilicon layer, a silicon nitride layer was etched to form it into a cell-defining layer. A polysilicon oxide dielectric cap was formed over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, the first polysilicon layer and the tunnel oxide layer were formed into a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Spacers are formed on the sidewalls of the gate electrode stack. Blanket inter-polysilicon dielectric and blanket control gate layers cover exposed portions of the substrate and the stack.

Abstract: A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.

Abstract: Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.

Abstract: Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.

Abstract: Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.

Abstract: In this invention polysilicon sidewalls on a semiconductor substrate are used as split gate flash memory cells. The sidewalls are formed around a core of silicon nitride and left standing once the silicon nitride is removed. Bit lines are implanted into the semiconductor substrate and extend partially under the sidewalls to allow the operation of the floating gates with respect to the buried bit line which act as drains and sources. A control gate is deposited over a row of sidewalls orthogonal to the bit lines and extending the length of a flash memory word line. The polysilicon sidewall split gate flash memory cells are programmed, read and erased by a combination of voltages applied to the control gate and the bit lines partially underlying the sidewalls.

Abstract: A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.