Abstract: A method is provided for forming a common self-aligned source line in order to reduce the number of surface contacts and at the same time alleviate the field oxide encroachment into the cell area. Thus, the size of the split-gate flash memory is substantially reduced on both accounts. This is accomplished by forming a buffer polysilicon layer over the floating gate to serve as an etch stop to protect the first poly-oxide of the floating gate during the self-aligned source etching.

Abstract: A select transistor for flash memory cells is made by the following steps. Over the blanket second dielectric layer, and an oxynitride layer form a channel mask for patterning the drain and floating gate. Etch the oxynitride layer through the mask to form a channel alignment mask down to a silicon nitride layer with a drain region opening and a floating gate opening. Etch the floating gate opening through the second dielectric layer. Form a polyoxide region in the floating gate layer at the bottom of the floating gate opening by reacting the exposed portion of the floating gate layer with a reactant. Form a drain region in the substrate. Etch away the oxynitride layer and the silicon nitride layer. Pattern the floating gate electrode by etching away the floating gate layer except below the polyoxide region. Form an interelectrode dielectric layer and a second gate electrode layer over the drain region and a portion of the polyoxide region.

Abstract: An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack.

Abstract: A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.

Abstract: A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes.

Abstract: A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form polyoxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird's beak that is formed at the edges of the polyoxide assumes a sharper shape with smaller size than that is found in prior art. This results in an increase in the erase speed of the memory cell.

Abstract: A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An interelectrode dielectric layer covers the floating gate electrodes, the sidewalls of the floating gate electrodes and the edges of the tunnel oxide below the floating gate electrodes. A second polysilicon layer overlies the interelectrode dielectric layer and is in turn covered by a tungsten silicide layer. A second dielectric layer covers the tungsten silicide layer. A control gate electrode which spans the pair of floating gate electrodes is formed by the second polysilicon layer, the tungsten silicide and the first and second dielectric layers patterned into a gate electrode stack providing a control gate electrode spanning across the pair of floating gate electrodes.

Abstract: An electrically erasable and programmable read only memory (EEPROM) is provided with an insulated control gate and an insulating floating gate in a trench in a semiconductor body. A dielectric layer is disposed along the sidewalls of the trench to separate the floating gate and the semiconductor body. The thickness of the dielectric layer along at least one sidewall of the trench is greater than the thickness of the dielectric layer along the other sidewalls of the trench in order to increase the programming speed due to a higher electric field in the gate oxide along the remaining sidewalls.

Abstract: An Erasable and Programmable Read Only Memory (EEPROM) cell is provided with an insulated control gate and an insulating floating gate formed in a trench in a semiconductor body. A surface-adjoining drain region is provided alongside an upper portion of a sidewall of the trench, while a source region is provided alongside a lower portion of the trench sidewall, with a channel region extending along the sidewall of the trench between the source and drain regions. The EEPROM cell is programmed by hot electron injection through the sidewall of the trench alongside the channel region, and is erased by Fowler Nordhiem tunneling through a corner region in the bottom of the trench by creating a localized high electric field density in the corner region. In this manner, a highly compact, efficient and durable EEPROM cell is obtained.