Patents by Inventor Dian-Hau Chen

Dian-Hau Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250143189
    Abstract: A first metal layer extends across memory and logic device regions of a semiconductor structure. A dielectric barrier layer is disposed over the first metal layer. A first dielectric layer is disposed over the dielectric barrier layer in the memory device region and not in the logic device region. Multiple magnetic tunneling junction (MTJ) devices are disposed in the memory device region. A second dielectric layer is disposed in the memory device region and not in the logic device region. The second dielectric layer is disposed over the first dielectric layer and the MTJ devices. An extreme low-k dielectric layer is disposed over the dielectric barrier layer in the logic device region. A conductive feature in the logic device region penetrates the extreme low-k dielectric layer and the dielectric barrier layer to electrically connect to the first metal layer.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Hsiang-Ku Shen, Dian-Hau Chen
  • Publication number: 20250140687
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method further includes forming a passivation layer over the interconnect structure. The method further includes forming a conductive structure over the passivation layer, wherein the conductive structure includes a surrounding portion over the passivation layer, and a concave portion surrounded by the surrounding portion. A height of the surrounding portion is greater than a height of the concave portion calculated from a top surface of the passivation layer. The method further includes forming a liner over the conductive structure, wherein an oxygen-to-silicon ratio of the liner is lower than about 1.8.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling CHANG, Chi-Hao CHANG, Hsiang-Ku SHEN, Dian-Hau CHEN
  • Publication number: 20250140722
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.
    Type: Application
    Filed: December 30, 2024
    Publication date: May 1, 2025
    Inventors: Chih-Fan Huang, Yen-Ming Chen, Chih-Sheng Li, Hui-Chi Chen, Chih-Hung Lu, Dian-Hau Chen
  • Publication number: 20250132246
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 24, 2025
    Inventors: Yi Ling Liu, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12266592
    Abstract: A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Yang Hsiao, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20250087639
    Abstract: A method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.
    Type: Application
    Filed: January 2, 2024
    Publication date: March 13, 2025
    Inventors: Ke-Gang Wen, Yu-Bey Wu, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12249531
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hsin Yang, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20250079339
    Abstract: Semiconductor devices having dummy regions with dummy fill structures that vary in lateral dimensions and methods for forming the semiconductor devices are provided herein. The semiconductor devices may include a through silicon via extending through a substrate of the semiconductor device, an active device in or on the substrate, and a dummy region of the substrate separating the through silicon via and the active device, the dummy region including dummy fill structures, wherein the dummy fill structures have lateral dimensions measured in a first direction from the through silicon via to the active device, wherein the lateral dimensions of the dummy fill structures varying in the first direction.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Nan Wang, Chih Hsin Yang, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12243909
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Dian-Hau Chen
  • Publication number: 20250070052
    Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming first gate structures around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a seal ring over the substrate, wherein the seal ring is between the first region and the second region.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 27, 2025
    Inventors: Ke-Gang Wen, Chih Hsin Yang, Kuan-Hsun Wang, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250070064
    Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.
    Type: Application
    Filed: January 3, 2024
    Publication date: February 27, 2025
    Inventors: Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Hsin-Feng Chen, Tsung-Chieh Hsiao, Chih Chuan Su, Dian-Hau Chen
  • Patent number: 12230566
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen
  • Publication number: 20250046667
    Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 6, 2025
    Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Chih-Pin Chiu, Hsin-Feng Chen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250038074
    Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: January 30, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Yun-Sheng Li, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12201031
    Abstract: Methods and devices are provided that include a magnetic tunneling junction (MTJ) element. A first spacer layer abuts sidewalls of the MTJ element. The first spacer layer has a low-dielectric constant (low-k) oxide composition. A second spacer layer is disposed on the first spacer layer and has a low-k nitride composition.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Ku Shen, Dian-Hau Chen
  • Publication number: 20250015007
    Abstract: One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Inventors: Yu-Chung Lai, Ying-Yao Lai, Chen-Chiu Huang, Hsiang-Ku Shen, Dian-Hau Chen, Kuo-An Liu, Tzu-Ting Liu
  • Patent number: 12191248
    Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Hsiang-Ku Shen, Dian-Hau Chen
  • Patent number: 12193336
    Abstract: A first metal layer extends across memory and logic device regions of a semiconductor structure. A dielectric barrier layer is disposed over the first metal layer. A first dielectric layer is disposed over the dielectric barrier layer in the memory device region and not in the logic device region. Multiple magnetic tunneling junction (MTJ) devices are disposed in the memory device region. A second dielectric layer is disposed in the memory device region and not in the logic device region. The second dielectric layer is disposed over the first dielectric layer and the MTJ devices. An extreme low-k dielectric layer is disposed over the dielectric barrier layer in the logic device region. A conductive feature in the logic device region penetrates the extreme low-k dielectric layer and the dielectric barrier layer to electrically connect to the first metal layer.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOE MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Ku Shen, Dian-Hau Chen
  • Patent number: 12183697
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Yen-Ming Chen, Chih-Sheng Li, Hui-Chi Chen, Chih-Hung Lu, Dian-Hau Chen
  • Publication number: 20240429156
    Abstract: A device includes a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions. A metal-insulator-metal (MIM) structure is embedded in the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer. The third dielectric layer and the second dielectric layer have different material compositions. The first dielectric layer or the third dielectric layer may contain silicon nitride (SiN), the second dielectric layer may contain silicon oxide (SiO2).
    Type: Application
    Filed: June 20, 2023
    Publication date: December 26, 2024
    Inventors: Chia-Yueh Chou, Hsiang-Ku Shen, Li-Chung Yu, Wen-Ling Chang, Chen-Chiu Huang, Dian-Hau Chen, Cheng-Hao Hou, Shin-Hung Tsai, Alvin Universe Tang, Kun-Yu Lee, Chun-Hsiu Chiang