Abstract: Methods and devices are provided that include a magnetic tunneling junction (MTJ) element. A first spacer layer abuts sidewalls of the MTJ element. The first spacer layer has a low-dielectric constant (low-k) oxide composition. A second spacer layer is disposed on the first spacer layer and has a low-k nitride composition.

Abstract: In an embodiment, a method includes forming active devices over a semiconductor substrate; forming an interconnect structure over the semiconductor substrate, the interconnect structure comprising a contact pad embedded in a dielectric layer; forming a first passivation layer over the interconnect structure; forming a first opening through the first passivation layer to expose the contact pad; depositing a seed layer over the first passivation layer and in the first opening; forming a sacrificial material over the seed layer; patterning the sacrificial material to reform the first opening and to form a second opening; depositing conductive material to form a first redistribution line in the first opening and a second redistribution line in the second opening; removing the sacrificial material; and attaching an integrated circuit die to the first redistribution line and the second redistribution line.

Abstract: In an embodiment, a device includes: a plurality of redistribution lines over a semiconductor substrate, the redistribution lines including trace portions extending along the semiconductor substrate; a first passivation layer over the redistribution lines, the first passivation layer filling an entirety of an area between the trace portions of the redistribution lines; a passive device over the first passivation layer; a dielectric layer over the passive device; and a die connector extending through the dielectric layer, the die connector physically and electrically coupled to the passive device.

Abstract: A first metal layer extends across memory and logic device regions of a semiconductor structure. A dielectric barrier layer is disposed over the first metal layer. A first dielectric layer is disposed over the dielectric barrier layer in the memory device region and not in the logic device region. Multiple magnetic tunneling junction (MTJ) devices are disposed in the memory device region. A second dielectric layer is disposed in the memory device region and not in the logic device region. The second dielectric layer is disposed over the first dielectric layer and the MTJ devices. An extreme low-k dielectric layer is disposed over the dielectric barrier layer in the logic device region. A conductive feature in the logic device region penetrates the extreme low-k dielectric layer and the dielectric barrier layer to electrically connect to the first metal layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method further includes forming a passivation layer over the interconnect structure. The method further includes forming a conductive structure over the passivation layer, wherein the conductive structure includes a surrounding portion over the passivation layer, and a concave portion surrounded by the surrounding portion. A height of the surrounding portion is greater than a height of the concave portion calculated from a top surface of the passivation layer. The method further includes forming a liner over the conductive structure, wherein an oxygen-to-silicon ratio of the liner is lower than about 1.8.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.

Abstract: The present disclosure provides a redistribution structure that includes a metal line, a first dielectric layer disposed over the metal line, a first etch stop layer (ESL) disposed over the first dielectric layer, a second dielectric layer disposed over the first ESL, and a conductive via extending through the second dielectric layer, the first ESL and the first dielectric layer to contact the metal line. A lower portion of the second dielectric layer extends downward through the first ESL and the first dielectric layer and partially into the metal line.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a substrate having a circuit region and a chip corner region; IC devices formed on the substrate within the circuit region; a passivation layer formed over the IC devices; and a polyimide layer formed over the passivation layer, wherein the passivation layer and the polyimide layer include a stress-release pattern formed in the chip corner region.

Abstract: A passivation layer is formed over an interconnect structure. An opening is etched at least partially through the passivation layer. A first conductive layer is deposited over the passivation layer. The first conductive layer partially fills the opening. An insulator layer is deposited over the first conductive layer. The insulator layer partially fills the opening. A second conductive layer is deposited over the insulator layer. The second conductive layer completely fills the opening. A first conductive structure is formed that is electrically coupled to the first conductive layer. A second conductive structure is formed that is electrically coupled to the second conductive layer.

Abstract: A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.

Abstract: Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers. The dielectric constant of the first layer is different than the dielectric constant of the second layer.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.

Abstract: A method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.

Abstract: Semiconductor devices having dummy regions with dummy fill structures that vary in lateral dimensions and methods for forming the semiconductor devices are provided herein. The semiconductor devices may include a through silicon via extending through a substrate of the semiconductor device, an active device in or on the substrate, and a dummy region of the substrate separating the through silicon via and the active device, the dummy region including dummy fill structures, wherein the dummy fill structures have lateral dimensions measured in a first direction from the through silicon via to the active device, wherein the lateral dimensions of the dummy fill structures varying in the first direction.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.

Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming first gate structures around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a seal ring over the substrate, wherein the seal ring is between the first region and the second region.

Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.