Patents by Inventor Dian-Hau Chen

Dian-Hau Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040089916
    Abstract: Within an option selection device structure and a method for fabrication thereof there is formed a terminal metal layer and an option selection device at a co-planar level over a microelectronic substrate. The option selection device is passivated with: (1) a terminal metal passivation layer having an etch stop layer within its thickness; and (2) a bond pad passivation layer. There is simultaneously also formed through the bond pad passivation layer: (1) a via which accesses a bond pad formed contacting the terminal metal layer; and (2) an aperture over the option selection device which stops at the etch stop layer.
    Type: Application
    Filed: November 13, 2002
    Publication date: May 13, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Juei-Kuo Wu, Yi-Lang Wu, Lin-June Wu, Dian-Hau Chen
  • Patent number: 6734116
    Abstract: Within a damascene method for forming a microelectronic fabrication, there is employed an etch stop layer comprising a comparatively low dielectric constant dielectric material sub-layer having formed thereupon a comparatively high dielectric constant dielectric material sub-layer. Within the method there is also simultaneously etched: (1) an anti-reflective coating layer from an inter-metal dielectric layer; and (2) the etch stop layer from a contact region. The microelectronic fabrication is formed with enhanced performance and enhanced reliability.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: May 11, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Cheng Guo, Dian-Hau Chen, Li-Kong Turn, Han-Ming Sheng
  • Publication number: 20040074872
    Abstract: A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectric layer when fabricating a complementary metal oxide semiconductor device.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 22, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Chen, Huan-Chi Tseng, Yu-Hua Lee, Dian-Hau Chen, Chia-Hung Lai, Kang-Min Kuo
  • Publication number: 20040013981
    Abstract: Within a method for fabricating a microelectronic fabrication there is employed a patterned positive photoresist residue layer as a protective layer within an aperture when processing an upper region of a topographic microelectronic layer having formed therein the aperture. The patterned positive photoresist residue layer is formed employing an incomplete vertical, but complete horizontal, blanket photoexposure and development of a blanket positive photoresist layer formed upon the topographic microelectronic layer and filling the aperture. The method provides the microelectronic fabrication with enhanced reliability.
    Type: Application
    Filed: July 16, 2002
    Publication date: January 22, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yong-Shun Liao, Juing-YI Wu, Dian-Hau Chen, Zhen-Cheng Chou
  • Patent number: 6667230
    Abstract: A method including the step of forming contact pads on a semiconductor wafer. A passivation blanket is deposited over the semiconductor wafer and the contact pads. The passivation blanket includes three layers. A first layer of silicon dioxide is deposited over the semiconductor wafer and the contact pads. A second layer of silicon nitride is deposited over the first layer, and a third layer and final layer of silicon dioxide is deposited over the second layer. The passivated semiconductor wafer is planarized using an oxide chemical mechanical planarization method. Holes are opened in the passivation blanket down to the contact pads. An under bump metallurgy is deposited onto the contact pads and a portion of the final silicon dioxide layer. Solder is deposited onto the under bump metallurgy and reflown to form a flip chip having solder bumps.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: December 23, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dian-Hau Chen, Lin-June Wu, Kwang-Ming Lin
  • Patent number: 6664194
    Abstract: There is first provided a substrate 10 and a target layer 12. There is then formed upon the target layer a patterned positive photoresist layer 14. There is then processed the target layer while employing the patterned positive photoresist layer as a mask layer, to thus form a processed target layer and a processed patterned positive photoresist layer. There is then photoexposed 18 the processed patterned positive photoresist layer to enhance its solubility. Finally, there is then stripped from the processed target layer the photoexposed processed patterned positive photoresist layer while employing a solvent.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: December 16, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Dian-Hau Chen, Chiang-Jen Peng, Wei-Kay Chiu
  • Patent number: 6652666
    Abstract: A wet dip method for photoresist and polymer stripping from a wafer surface without the need for a buffer solvent treatment step is disclosed. In the method, the wafer is first exposed to an etchant solution that is maintained at a temperature of at least 80° C. The wafer is then cooled in a room temperature air for a sufficient length of time until the temperature of the wafer reaches substantially room temperature. The wafer is then rinsed in a rinsing step that includes a quick dump rinse and a final rinse with deionized water that is maintained at a temperature not higher than room temperature without first exposing the wafer to a buffer solvent such as that required in a conventional wet dip method.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: November 25, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd
    Inventors: Ching-Tien Ma, Chen-Hsi Shih, Dian-Hau Chen, Gau-Ming Lu, Cho-Ching Chen
  • Publication number: 20030134521
    Abstract: Within a damascene method for forming a microelectronic fabrication, there is employed an etch stop layer comprising a comparatively low dielectric constant dielectric material sub-layer having formed thereupon a comparatively high dielectric constant dielectric material sub-layer. Within the method there is also simultaneously etched: (1) an anti-reflective coating layer from an inter-metal dielectric layer; and (2) the etch stop layer from a contact region. The microelectronic fabrication is formed with enhanced performance and enhanced reliability.
    Type: Application
    Filed: January 11, 2002
    Publication date: July 17, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Cheng Guo, Dian-Hau Chen, Li-Kong Turn, Han-Ming Sheng
  • Patent number: 6570257
    Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: May 27, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Dian-Hau Chen, Ching-Tien Ma, Hsiang-Tan Lee
  • Patent number: 6551927
    Abstract: A cobalt silicide process having a titanium-rich/titanium nitride capping layer to improve junction leakage is described. Semiconductor device structures to be silicided are formed in and on a semiconductor substrate. A cobalt layer is deposited overlying the semiconductor device structures. A titanium-rich/titanium nitride capping layer is deposited overlying the cobalt layer. Thereafter, a cobalt silicide layer is formed on the semiconductor device structures. The titanium-rich/titanium nitride capping layer and an unreacted portion of the cobalt layer are removed to complete fabrication of the integrated circuit device.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: April 22, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Dian-Hau Chen, Kwang-Ming Lin, Yu-Ku Lin, Tong-Hua Kuan, Jin-Kuen Lan
  • Publication number: 20030013291
    Abstract: A method including the step of forming contact pads on a semiconductor wafer. A passivation blanket is deposited over the semiconductor wafer and the contact pads. The passivation blanket includes three layers. A first layer of silicon dioxide is deposited over the semiconductor wafer and the contact pads. A second layer of silicon nitride is deposited over the first layer, and a third layer and final layer of silicon dioxide is deposited over the second layer. The passivated semiconductor wafer is planarized using an oxide chemical mechanical planarization method. Holes are opened in the passivation blanket down to the contact pads. An under bump metallurgy is deposited onto the contact pads and a portion of the final silicon dioxide layer. Solder is deposited onto the under bump metallurgy and reflown to form a flip chip having solder bumps.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 16, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dian-Hau Chen, Lin-June Wu, Kwang-Ming Lin
  • Patent number: 6489216
    Abstract: Within a chemical mechanical polish (CMP) planarizing method for forming a planarized layer there is first provided a microelectronic substrate having a topographic mark formed therein. There is then formed over the microelectronic substrate and covering the topographic mark a blanket conformal layer which forms a replicated topographic mark at the location of the topographic mark. There is then formed over the blanket conformal layer and the replicated topographic mark a patterned negative photoresist layer of areal dimensions minimally sufficient to encapsulate the replicated topographic mark. There is then chemical mechanical polish (CMP) planarized the patterned negative photoresist layer and the blanket conformal layer to form a chemical mechanical polish (CMP) planarized patterned negative photoresist layer and a chemical mechanical polish (CMP) planarized blanket conformal microelectronic layer.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: December 3, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Ruei-Je Shiu, Dian-Hau Chen
  • Publication number: 20020162578
    Abstract: A wet dip method for photoresist and polymer stripping from a wafer surface without the need for a buffer solvent treatment step is disclosed. In the method, the wafer is first exposed to an etchant solution that is maintained at a temperature of at least 80° C. The wafer is then cooled in a room temperature air for a sufficient length of time until the temperature of the wafer reaches substantially room temperature. The wafer is then rinsed in a rinsing step that includes a quick dump rinse and a final rinse with deionized water that is maintained at a temperature not higher than room temperature without first exposing the wafer to a buffer solvent such as that required in a conventional wet dip method.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 7, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Ching-Tien Ma, Chen-Hsi Shih, Dian-Hau Chen, Gau-Ming Lu, Cho-Ching Chen
  • Publication number: 20020164878
    Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas? Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.
    Type: Application
    Filed: July 1, 2002
    Publication date: November 7, 2002
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chiang Jen Peng, Dian Hau Chen
  • Patent number: 6468904
    Abstract: A method for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas wherein at least one device area is to be silicided and wherein at least one device area is not to be silicided. A composite resist protective oxide layer is formed overlying device areas comprising a first layer of oxide and a second layer of silicon oxynitride. The silicon oxynitride layer is dry etched away overlying the device area to be silicided. Thereafter, the oxide layer is wet etched away overlying the device area to be silicided. Silicidation is performed to complete fabrication of the integrated circuit device.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: October 22, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Dian-Hau Chen, Fu-Mei Chiu, Lin-June Wu
  • Patent number: 6429142
    Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas. Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: August 6, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chiang Jen Peng, Dian Hau Chen
  • Publication number: 20020013024
    Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.
    Type: Application
    Filed: October 9, 2001
    Publication date: January 31, 2002
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Dian-Hau Chen, Ching-Tien Ma, Hsiang-Tan Lee
  • Patent number: 6316351
    Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: November 13, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Dian-Hau Chen, Ching-Tien Ma, Hsiang-Tan Lee