Abstract: A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

Abstract: In a method of manufacturing a semiconductor device, a cell structure is formed. The cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode and a hard mask layer disposed on the MTJ stack. A first insulating cover layer is formed over sidewall of the MTJ stack. A second insulating cover layer is formed over the first insulating cover layer and the hard mask layer. A first interlayer dielectric (ILD) layer is formed. The hard mask layer is exposed by etching the first ILD layer and the second insulating cover layer. A second ILD layer is formed. A contact opening is formed in the second ILD layer by patterning the second ILD layer and removing the hard mask layer. A conductive layer is formed in the contact opening so that the conductive layer contacts the MTJ stack.

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, an interconnect structure, a memory cell and a conductive via. The semiconductor substrate has a first side and a second side opposite to the first side. The gate structure is disposed over the first side of the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate aside the gate structure. The interconnect structure is disposed over the first side of the semiconductor substrate and electrically connected to the source region. The memory cell is disposed over the second side of the semiconductor substrate and electrically connected to the drain region. The conductive via is disposed in the semiconductor substrate between the drain region and the memory cell and electrically connects the drain region and the memory cell.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.

Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a second electrode layer formed over the first electrode layer, and a second spacer formed on a sidewall of the second electrode layer. The second spacer is in direct contact with an interface between the second electrode layer and a first dielectric layer.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

Abstract: Methods and devices are provided that include a magnetic tunneling junction (MTJ) element. A first spacer layer abuts sidewalls of the MTJ element. The first spacer layer has a low-dielectric constant (low-k) oxide composition. A second spacer layer is disposed on the first spacer layer and has a low-k nitride composition.

Abstract: A method includes providing a structure having a memory region and a logic region; a first metal layer and a dielectric barrier layer over the first metal layer in both the memory region and the logic region; a first dielectric layer over the dielectric barrier layer; multiple magnetic tunneling junction (MTJ) devices over the first metal layer, the dielectric barrier layer, and the first dielectric layer; and a second dielectric layer over the first dielectric layer and the MTJ devices. The first dielectric layer, the MTJ devices, and the second dielectric layer are in the memory device region and not in the logic device region. The method further includes depositing an extreme low-k (ELK) dielectric layer using FCVD over the memory region and the logic region; and buffing the ELK dielectric layer to planarize a top surface of the ELK dielectric layer.

Abstract: The present disclosure is directed to a method of fabrication a semiconductor structure. The method includes providing a substrate and forming a bottom electrode over the substrate, wherein a terminal end of the bottom electrode has a tapered sidewall. The method also includes depositing an insulating layer over the bottom electrode and forming a top electrode over the insulating layer, wherein a terminal end of the top electrode has a vertical sidewall.

Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.