Abstract: A dartboard structure and a method for manufacturing the dartboard structure are provided. The dartboard structure includes a dartboard body unit, a dartboard frame unit, a first sensor unit and a second sensor unit. The dartboard body unit has a plurality of score regions. The dartboard frame unit has a plurality of through openings that penetrate through the dartboard frame unit, and each of the through openings corresponds to one of the score regions. The second sensor unit and the first sensor unit are in an intersecting arrangement and have a predetermined gap therebetween. The first sensor unit and the second sensor unit surround a plurality of first sensing regions, and each of the first sensing regions corresponds to one of the score regions and one of the through openings.

Abstract: An electronic darting system, a processing method for an electronic darts game, and a dartboard device are provided. The electronic darting system includes a dartboard device, a tip unit, and an image providing device. The dartboard device includes a dartboard case, a plurality of induction circuits, and a control circuit. The dartboard case includes a board surface. The plurality of induction circuits are disposed on the board surface, and the plurality of induction circuits are intersecting with each other to form a plurality of induction areas of a plurality of target areas of the board surface. The image providing device provides a plurality of images onto the board surface of the dartboard case.

Abstract: A magnetic induction dart and a magnetic induction darting system are provided. The magnetic induction dart includes a barrel, a tip unit, and a magnetic unit. The first terminal and the second terminal of the barrel are oppositely disposed. The first terminal of the barrel has a recess. The tip unit is disposed at the first terminal of the barrel. The magnetic unit is disposed in the recess of the first terminal of the barrel. The tip unit is fixedly disposed in the barrel. The tip unit is in contact with the magnetic unit in the recess. The first terminal of the barrel further includes a first fixing structure. A first end of the tip unit includes a second fixing structure. The tip unit is fixedly connected to the first fixing structure of the barrel through the second fixing structure.

Abstract: A dartboard structure and a method for manufacturing the dartboard structure are provided. The dartboard structure includes a dartboard body unit, a dartboard frame unit, a first sensor unit and a second sensor unit. The dartboard body unit has a plurality of score regions. The dartboard frame unit has a plurality of through openings that penetrate through the dartboard frame unit, and each of the through openings corresponds to one of the score regions. The second sensor unit and the first sensor unit are in an intersecting arrangement and have a predetermined gap therebetween. The first sensor unit and the second sensor unit surround a plurality of first sensing regions, and each of the first sensing regions corresponds to one of the score regions and one of the through openings.

Abstract: A chip packaging structure and a manufacturing method for the same are provided. The chip packaging structure includes a first chip, a second chip and a transfer component. The first chip has a plurality of first bonding pads formed on the top surface of the first chip. The second chip has a plurality of second bonding pads formed on the top surface of the second chip. The first chip and the second chip are arranged abreast and electrically connected to each other. The transfer component is disposed on the top surface of the first chip and electrically connected with the first chip. Via these arrangements, the chip packaging structure can have smaller dimensions.

Abstract: A semiconductor packaging structure and a manufacturing method for the same are disclosed. The semiconductor packaging structure includes a chip, a dielectric layer and a plurality of redistribution circuit layers. The chip has a plurality of connection pads. The dielectric layer is disposed on the chip and defined with a plurality of containers therein. The connection pads are exposed from the containers, respectively. The redistribution circuit layers are disposed within the containers and electrically connected with the connection pads, respectively. Via these arrangements, the bonding surfaces between the redistribution circuit layers and the dielectric layer can be increased.

Abstract: A meal top stacking package structure and a method for manufacturing the same are provided, wherein the metal top stacking package structure includes a metal base including an upper surface and a lower surface, and a die receiver cavity formed in the upper surface; a first chip fixed on the die receiver cavity by a first adhesion layer; a substrate with an upper surface; a second chip fixed on the upper surface of the substrate by a second adhesion layer; and a plurality of connecting components formed on the upper surface of the substrate; wherein the upper surface of the metal base is connected with the substrate by the connecting components. Thereby, the structure and method can enhance heat dissipation and electromagnetic shield of the stacking package structure.

Abstract: A packaging structure for thin die is provided. The packaging structure has a substrate, a thin die, a strengthening layer and an encapsulation body. The thin die is disposed on and electrically connected with the substrate; the strengthening layer is disposed on the thin die; and the encapsulation body is formed on the substrate and covers both the thin die and the strengthening layer. The strengthening layer can bear pressure or stress during the formation of the encapsulation body to protect the thin die. A method for manufacturing the packaging structure for the thin die is further provided to manufacture the above packaging structure for the thin die.

Abstract: A lead frame structure for quad flat no-lead (QFN) package includes a main base, a plurality of terminals and a first metal layer. The main base has a center area for carrying a semiconductor die, and a periphery area surrounding the center area. The plurality of terminals are arranged around the main base. The first metal layer has a first part formed on the periphery area of the main base, and a second part formed on the plurality of terminals. Wherein the main base and the plurality of terminals are formed by a stamping process, and the first metal layer is formed by a plating process before the stamping process.

Abstract: The present invention relates to a meal top stacking package structure and a method for manufacturing the same, wherein the metal top stacking package structure comprises a metal base including an upper surface and a lower surface, and a die receiver cavity formed in the upper surface; a first chip fixed on the die receiver cavity by a first adhesion layer; a substrate with an upper surface; a second chip fixed on the upper surface of the substrate by a second adhesion layer; and a plurality of connecting components formed on the upper surface of the substrate; wherein the upper surface of the metal base is connected with the substrate by the connecting components. Thereby, the structure and method can enhance heat dissipation and electromagnetic shield of the stacking package structure.

Abstract: The present invention relates to a multichip stacking package structure and a method for manufacturing the same, wherein the multichip stacking package structure comprises a substrate including a plurality of electrical connecting pad; a first chip with a lower surface stacked on the substrate; a second chip stacked on an upper surface of the first chip by a interlaced reciprocation stacking way; a spacer stacked on an upper surface of the second chip by the interlaced reciprocation stacking way; and third chip stacked on the an upper surface of the spacer by the interlaced reciprocation stacking way, so that a first spacing is formed between an end of the third and an end of the spacer. Thereby, a position of a stress point is changed to reduce a risk of the chip crack during wire bonding.

Abstract: The present invention relates to a multichip stacking package structure and a method for manufacturing the same, wherein the multichip stacking package structure comprises a substrate including a plurality of electrical connecting pad; a first chip with a lower surface stacked on the substrate; a second chip stacked on an upper surface of the first chip by a interlaced reciprocation stacking way; a spacer stacked on an upper surface of the second chip by the interlaced reciprocation stacking way; and third chip stacked on the an upper surface of the spacer by the interlaced reciprocation stacking way, so that a first spacing is formed between an end of the third and an end of the spacer. Thereby, a position of a stress point is changed to reduce a risk of the chip crack during wire bonding.

Abstract: A packaging structure for thin die is provided. The packaging structure has a substrate, a thin die, a strengthening layer and an encapsulation body. The thin die is disposed on and electrically connected with the substrate; the strengthening layer is disposed on the thin die; and the encapsulation body is formed on the substrate and covers both the thin die and the strengthening layer. The strengthening layer can bear pressure or stress during the formation of the encapsulation body to protect the thin die. A method for manufacturing the packaging structure for the thin die is further provided to manufacture the above packaging structure for the thin die.

Abstract: A micro electronic component structure includes an insulating body, at least one conductive through hole, at least one conductive material, and at least one micro terminal. The insulating body has a top surface and a bottom surface. The conductive through hole penetrates the top surface and the bottom surface. The conductive material is formed in the conductive through hole. The micro terminal is disposed above the conductive material.

Abstract: A semiconductor packaging structure and a manufacturing method for the same are disclosed. The semiconductor packaging structure includes a chip, a dielectric layer and a plurality of redistribution circuit layers. The chip has a plurality of connection pads. The dielectric layer is disposed on the chip and defined with a plurality of containers therein. The connection pads are exposed from the containers, respectively. The redistribution circuit layers are disposed within the containers and electrically connected with the connection pads, respectively. Via these arrangements, the bonding surfaces between the redistribution circuit layers and the dielectric layer can be increased.

Abstract: A lead frame structure for quad flat no-lead (QFN) package includes a main base, a plurality of terminals and a first metal layer. The main base has a center area for carrying a semiconductor die, and a periphery area surrounding the center area. The plurality of terminals are arranged around the main base. The first metal layer has a first part formed on the periphery area of the main base, and a second part formed on the plurality of terminals. Wherein the main base and the plurality of terminals are formed by a stamping process, and the first metal layer is formed by a plating process before the stamping process.

Abstract: A method for manufacturing a chip packaging structure is disclosed. The manufacturing method includes steps of: providing a protection layer; forming a conductive trace layer on the protection layer; forming an adhesion layer on the conductive trace layer; placing a chip on the adhesion layer; and electrically connecting the chip to the conductive trace layer. Via these arrangements, the chip packaging structure made by the manufacturing method can have a smaller thickness.

Abstract: A micro electronic component structure includes an insulating body, at least one conductive through hole, at least one conductive material, and at least one micro terminal. The insulating body has a top surface and a bottom surface. The conductive through hole penetrates the top surface and the bottom surface. The conductive material is formed in the conductive through hole. The micro terminal is disposed above the conductive material.

Abstract: The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes an dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying with the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.

Abstract: A chip packaging structure and a manufacturing method for the same are provided. The chip packaging structure includes a first chip, a second chip and a transfer component. The first chip has a plurality of first bonding pads formed on the top surface of the first chip. The second chip has a plurality of second bonding pads formed on the top surface of the second chip. The first chip and the second chip are arranged abreast and electrically connected to each other. The transfer component is disposed on the top surface of the first chip and electrically connected with the first chip. Via these arrangements, the chip packaging structure can have smaller dimensions.