Abstract: In accordance with an embodiment, a system includes a programmable gain amplifier having a switchable feedback capacitor coupled in parallel with a first capacitor and a controller. The controller is configured to couple the feedback capacitor between an input node of the programmable gain amplifier and an output node of the programmable gain amplifier in a first gain setting, and switch a first terminal of the feedback capacitor from the output of the programmable gain amplifier to a reference node while a second terminal of the feedback capacitor remains coupled to the input node of the programmable gain amplifier for a first time period when transitioning from the first gain setting to a second gain setting.

Abstract: An apparatus for generating a sensor signal indicating information on a capacitance of a variable capacitor including a variable capacitance includes a sensor unit and a compensation unit. The sensor unit is configured to generate a sensor signal indicating information on a varying current flowing through a connection between the sensor unit and the variable capacitor caused by a variation of the capacitance of the variable capacitor while the variable capacitor is biased by a predefined bias voltage. Further, the compensation unit is configured to influence the sensor signal or to provide a compensation signal capable of influencing the sensor signal so that the sensor signal includes less nonlinear signal portions than a sensor signal without the influence of the compensation unit or the compensation signal.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: Apparatuses and methods are described where input signals are supplied to a translinear mesh. In some embodiments an output of the translinear mesh is regulated to a desired value.

Abstract: Representative implementations of devices and techniques provide a linearized high-ohmic resistor. In an example, a quantity of serially connected nonlinear impedances is arranged as a resistance. In one example, the quantity of impedances is applied in an amplifier circuit, between an input of the amplifier and an output of the amplifier, and arranged to set a DC operating point for the amplifier.

Abstract: In accordance with an embodiment, a system includes a programmable gain amplifier having a switchable feedback capacitor coupled in parallel with a first capacitor and a controller. The controller is configured to couple the feedback capacitor between an input node of the programmable gain amplifier and an output node of the programmable gain amplifier in a first gain setting, and switch a first terminal of the feedback capacitor from the output of the programmable gain amplifier to a reference node while a second terminal of the feedback capacitor remains coupled to the input node of the programmable gain amplifier for a first time period when transitioning from the first gain setting to a second gain setting.

Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

Abstract: In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

Abstract: Implementations to mitigating side effects of impedance transformation circuits are described. In particular, mitigation circuitry may be coupled to a high impedance circuit to minimize or eliminate non-linear output of the high impedance circuit in order to provide a well-defined bias voltage to the input of a buffer or amplifier device coupled to a capacitive sensor. Additionally, the mitigation circuitry may be coupled to the high impedance circuit to reduce or eliminate rectifying effects of the high impedance circuit. Accordingly, a bias voltage can be utilized to provide a stable operating point of the buffer or amplifier device via a high impedance circuit utilizing one or more impedance transformations.

Abstract: In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: This disclosure describes at least one class AB amplifier output stage circuit arrangement that can operate at low supply voltages, with minimum current generated. Furthermore, at least one class AB amplifier stage circuit arrangement described herein reacts favorably to a supply voltage, that is, exhibits a good power supply rejection ratio. Moreover, this disclosure describes class AB amplifier output stage circuit arrangements that include a negative channel metal oxide semiconductor (NMOS) transistor current mirror arrangement and a positive channel metal oxide semiconductor (PMOS) transistor current mirror arrangement. In some implementations, a monitoring circuit may be coupled to a class AB amplifier output stage circuit arrangement to offset mismatch that may occur in the class AB amplifier output stage.

Abstract: Systems and methods for implementing an up-conversion mixer with signal processing are disclosed.

Abstract: Systems and methods for implementing a down-conversion mixer with signal processing are disclosed.

Abstract: In accordance with an embodiment, a method of driving switches includes sensing a control node of a first switch, sensing a control node of a second switch, and driving the control node of the first switch to a first active state after the control node of the second switch transitions to a second active state. The method also includes driving the control node of the second switch to a second inactive state after the control node of the first switch transitions to a first inactive state. Driving the control node of the first switch is based on sensing the control node of the second switch, and driving the control node of the second switch is based on based on sensing the control node of the first switch.

Abstract: In accordance with an embodiment, a circuit for driving a switch includes a driver circuit. The driver circuit includes a first output configured to be coupled to a gate of the JFET, a second output configured to be coupled to a gate of the MOSFET, a first power supply node, and a bias input configured to be coupled to the common node. The switch to be driven includes a JFET coupled to a MOSFET at a common node.

Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.