Patents by Inventor Dieter Härle
Dieter Härle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11443990Abstract: In some examples, a device includes a power structure and a sensing structure that is electrically isolated from the power structure. The device also includes processing circuitry configured to determine whether the sensing structure includes a prognostic health indicator, wherein the prognostic health indicator is indicative of a health of the power structure.Type: GrantFiled: June 29, 2020Date of Patent: September 13, 2022Assignee: Infineon Technologies AGInventors: Sergio De Gasperi, Michael Nelhiebel, Alexander Mayer, Dieter Haerle, Andrea Baschirotto
-
Publication number: 20210407870Abstract: In some examples, a device includes a power structure and a sensing structure that is electrically isolated from the power structure. The device also includes processing circuitry configured to determine whether the sensing structure includes a prognostic health indicator, wherein the prognostic health indicator is indicative of a health of the power structure.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Inventors: Sergio De Gasperi, Michael Nelhiebel, Alexander Mayer, Dieter Haerle, Andrea Baschirotto
-
Patent number: 11182525Abstract: A fault aware analog model (FAAM) system is disclosed. The FAAM system comprises a FAAM builder module comprising a model construction module configured to receive a reference dataset associated with a circuit block. The reference dataset comprises a set of data values that defines input to output relationship of the circuit block for both in spec and out of spec operation of the circuit block. The reference data set is derived based on data associated with a ground truth representation of the circuit block. In some embodiments, the model construction module is further configured to generate a FAAM comprising a behavioral model of the circuit block, based on the reference dataset, wherein the FAAM is configured to approximate the input to output relationship of the circuit block that is defined by the set of data values in the reference dataset.Type: GrantFiled: July 7, 2020Date of Patent: November 23, 2021Assignee: Infineon Technologies AGInventors: Ahmed Sokar, Dieter Haerle, Petar Tzenov, Anis Chenbeh
-
Patent number: 10122369Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: GrantFiled: April 5, 2017Date of Patent: November 6, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: Peter Vlasenko, Dieter Haerle
-
Publication number: 20170272085Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: April 5, 2017Publication date: September 21, 2017Inventors: Peter Vlasenko, Dieter Haerle
-
Publication number: 20140225651Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: Conversant Intellectual Property Management Inc.Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
-
Patent number: 8704569Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: December 18, 2012Date of Patent: April 22, 2014Assignee: MOSAID Technologies IncorporatedInventors: Dieter Haerle, Tony Mai, Peter Vlasenko
-
Publication number: 20140084977Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: November 27, 2013Publication date: March 27, 2014Applicant: MOSAID Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
-
Patent number: 8599984Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: GrantFiled: March 26, 2013Date of Patent: December 3, 2013Assignee: MOSAID Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
-
Patent number: 8411812Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: GrantFiled: June 14, 2012Date of Patent: April 2, 2013Assignee: Mosaid Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
-
Publication number: 20130003483Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: June 14, 2012Publication date: January 3, 2013Applicant: MOSAID Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
-
Patent number: 8222937Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.Type: GrantFiled: October 27, 2011Date of Patent: July 17, 2012Assignee: Mosaid Technologies IncorporatedInventor: Dieter Haerle
-
Patent number: 8213561Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: GrantFiled: July 19, 2011Date of Patent: July 3, 2012Assignee: Mosaid Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
-
Publication number: 20120098581Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.Type: ApplicationFiled: October 27, 2011Publication date: April 26, 2012Applicant: MOSAID Technologies IncorporatedInventor: Dieter Haerle
-
Publication number: 20110291721Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: July 19, 2011Publication date: December 1, 2011Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventors: Peter Vlasenko, Dieter Haerle
-
Patent number: 8049541Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.Type: GrantFiled: January 7, 2011Date of Patent: November 1, 2011Assignee: Mosaid Technologies IncorporatedInventor: Dieter Haerle
-
Patent number: RE43552Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.Type: GrantFiled: February 19, 2010Date of Patent: July 24, 2012Assignee: Mosaid Technologies IncorporatedInventors: Alan Roth, Sean Lord, Robert McKenzie, Dieter Haerle, Steven Smith
-
Patent number: RE43947Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: May 11, 2011Date of Patent: January 29, 2013Assignee: Mosaid Technologies IncorporatedInventors: Dieter Haerle, Tony Mai, Peter Vlasenko
-
Patent number: RE47715Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.Type: GrantFiled: July 17, 2014Date of Patent: November 5, 2019Assignee: Conversant Intellectual Property Management Inc.Inventor: Dieter Haerle
-
Patent number: RE49018Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.Type: GrantFiled: May 9, 2019Date of Patent: April 5, 2022Assignee: Mosaid Technologies IncorporatedInventor: Dieter Haerle