Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Abstract: A circuit and method for capacitor effective series resistance measurement. One embodiment provides a method for measuring the effective series resistance of a capacitor having a capacitor voltage. The method includes amplifying the capacitor voltage with an AC coupled amplifier yielding a first amplified signal. The capacitor is discharged with a constant current for a measurement time thus causing a voltage swing of the capacitor voltage due to a voltage drop across the effective series resistance. The capacitor voltage is amplified with the AC coupled amplifier yielding a second amplified signal being dependent on the voltage swing. The effective series resistance is calculated from the first and the second amplified signals.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Abstract: A drive circuit for a firing element of an occupant protection system comprises first and second supply potential terminals and first and second firing element terminals. A first semiconductor switching element is integrated in a first semiconductor body and has a first load terminal coupled to the first supply potential terminal and a second load terminal coupled to the first firing element terminal. A second semiconductor switching element is integrated in a second semiconductor body and has a first load terminal coupled to the second firing element terminal and a second load terminal coupled to the second supply potential terminal. The first and second semiconductor bodies are applied to a thermally conductive carrier element and commonly housed. A temperature detector is integrated in the second semiconductor body and provides an overtemperature signal at an output of the drive circuit upon detection of an overtemperature of the first semiconductor switching element.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The charge pump further includes a pull-up circuit and a pull-down circuit coupled to the operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Abstract: A charge pump for use in a locked loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. The charge pump further includes a startup circuit to establish a predetermined voltage level at the charge pump output node during startup.

Abstract: A circuit and method for capacitor effective series resistance measurement. One embodiment provides a method for measuring the effective series resistance of a capacitor having a capacitor voltage. The method includes amplifying the capacitor voltage with an AC coupled amplifier yielding a first amplified signal. The capacitor is discharged with a constant current for a measurement time thus causing a voltage swing of the capacitor voltage due to a voltage drop across the effective series resistance. The capacitor voltage is amplified with the AC coupled amplifier yielding a second amplified signal being dependent on the voltage swing; calculating the effective series resistance from the first and the second amplified signal.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operations amplifier also mitigates the effects of low power supply voltage.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

Abstract: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

Abstract: A charge pump for use in a Phase Locked Loop/Delay Locked Loop. The charge pump includes a pull-up circuit a pull-down circuit and a reference current source. The reference current source includes a number of select transistors and a number of mirror master transistors. The mirror master transistors are coupled to slave transistors in either of the pull-up circuit and the pull-down circuit.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

Abstract: A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.