Abstract: A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns.

Abstract: A semiconductor device including a drift zone of a first conductivity type serving as a substrate layer having a front side and a back side. A first contact electrode is arranged at the front side of the drift zone. A control region is arranged at the front side and controls an injection of carriers of at least the first conductivity type into the drift zone. A second contact electrode is arranged at the backside of the drift zone. The drift zone is arranged to carry a carrier flow between the first and the second contact electrode. The drift zone includes a silicon carbide wafer with a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns.

Abstract: A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5×1014 cm?3, and a concentration of transition metals impurities less than 5×1014 cm?3. Intrinsic defects in the crystal are minimised. The intrinsic defects include silicon vacancies or carbon vacancies. The crystal is annealed for a desired time at a temperature above 700° C. in an atmosphere containing any of the gases hydrogen or a mixture of hydrogen and an inert gas, such that the density of intrinsic defects and any associated defects is decreased to a concentration low enough to confer to the crystal a desired carrier life time of at least 50 ns at room temperature.

Abstract: An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and at least one thin intermediate layer of the first conductivity type. The intermediate layer is arranged inside the drift zone, has a higher doping concentration than the drift zone, and divides the drift zone into at least one first anode-side drift zone layer and at least one second cathode-side drift zone layer. There is also disclosed a circuit configuration with such SiC—PN power diodes.

Abstract: A method for manufacturing a silicon carbide single crystal. A silicon carbide single crystal is grown. The crystal has a boron concentration less than 5×1014 cm?3, and a concentration of transition metals impurities less than 5×1014 cm?3. Intrinsic defects in the crystal are minimised. The intrinsic defects include silicon vacancies or carbon vacancies. The crystal is annealed for a desired time at a temperature above 700° C. in an atmosphere containing any of the gases hydrogen or a mixture of hydrogen and an inert gas, such that the density of intrinsic defects and any associated defects is decreased to a concentration low enough to confer to the crystal a desired carrier life time of at least 50 ns at room temperature.

Abstract: A uniform silicon carbide single crystal with either an n-type or a p-type conductivity. The crystal has a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns at room temperature.

Abstract: An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and at least one thin intermediate layer of the first conductivity type. The intermediate layer is arranged inside the drift zone, has a higher doping concentration than the drift zone, and divides the drift zone into at least one first anode-side drift zone layer and at least one second cathode-side drift zone layer. There is also disclosed a circuit configuration with such SiC—PN power diodes.

Abstract: A uniform silicon carbide single crystal with either an n-type or a p-type conductivity. The crystal has a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns at room temperature.

Abstract: A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: The disclosed semiconductor device comprises an ohmic contact between a semiconductor region made of n-conducting silicon carbide and a largely homogeneous ohmic contact layer (110), which adjoins the semiconductor region and is made of a material having a first and a second material component. A silicide formed from the first material component and the silicon of the silicon carbide and a carbide formed from the second material component and the carbon of the silicon carbide are contained in a junction region between the semiconductor region and the ohmic contact layer. The silicide and carbide formation take place at maximum 1000° C.

Abstract: The semiconductor configuration is formed with a lateral channel region and an adjoining vertical channel region in an n-conductive first semiconductor region. When a predetermined saturation current is exceeded, the lateral channel region is pinched off and the current is limited to a value below the saturation current.

Abstract: A silicon-based semiconductor component includes a high-efficiency barrier junction termination. In the semiconductor component, a silicon semiconductor region takes on the depletion region of an active area of the semiconductor component. The junction termination for the active area is formed with silicon with a doping that is opposite to that of the semiconductor region, and the junction termination surrounds the active area on or in a surface of the semiconductor region. The junction termination is doped with a dopant that has a low impurity energy level of at least 0.1 eV in silicon. Preferably Be, Zn, Ni, Co, Mg, Sn or In are used as acceptors and S, Se or Ti are provided as donors.

Abstract: An electronic switching device includes at least one first and one second semiconductor component, with a first anode connection and a second cathode connection being short-circuited. A control voltage that can be applied to a first grid connection is also at least partially present at a second grid connection. This reduces the forward resistance of the electronic switching device in the switched-on state.

Abstract: A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.

Abstract: A semiconductor structure includes at least one &agr;-silicon carbide region and an electrically insulating region, e.g. made of an oxide layer, and an interface located between them. The selection of an &agr;-silicon carbide polytype having a smaller energy gap than that of the 6H silicon carbide polytype for at least one region near the interface results in a high charge carrier mobility in this region.

Abstract: An electronic switching device includes at least one first and one second semiconductor component, with a first anode connection and a second cathode connection being short-circuited. A control voltage that can be applied to a first grid connection is also at least partially present at a second grid connection. This reduces the forward resistance of the electronic switching device in the switched-on state.

Abstract: The disclosed semiconductor device comprises an ohmic contact between a semiconductor region made of n-conducting silicon carbide and a largely homogeneous ohmic contact layer (110), which adjoins the semiconductor region and is made of a material having a first and a second material component. A silicide formed from the first material component and the silicon of the silicon carbide and a carbide formed from the second material component and the carbon of the silicon carbide are contained in a junction region between the semiconductor region and the ohmic contact layer. The silicide and carbide formation take place at maximum 1000° C.

Abstract: A semiconductor configuration, in particular based on silicon carbide, is specified which rapidly limits a short-circuit current to an acceptable current value. For this purpose, when a predetermined saturation current is exceeded, a lateral channel region is pinched off, and the current is limited to a value below the saturation current.