Abstract: Abnormal generation of heat of a power MOSFET is detected to improve the reliability of a semiconductor device. As its means, in a power MOSFET having a drain electrode on the side of a back surface of a semiconductor substrate and a source pad on the side of a main surface of the semiconductor substrate, two gate pads electrically connected to a gate pad connected to a gate electrode of the power MOSFET are formed on the side of the main surface of the semiconductor substrate. Further, there is provided a voltmeter connected in parallel with each of two current paths which connect the two gate pads and a gate driver.

Abstract: A quantum bit array including a plurality of quantum dots capable of confining a quantum bit and a plurality of gate electrodes used to control of the plurality of quantum dots, and a control device controlling a plurality of quantum bits using the plurality of gate electrodes, the quantum bit array includes a storage region including a plurality of quantum dots storing the quantum bit, and an operation region including a plurality of quantum dots capable of applying a quantum gate operation of changing a spin state to the confined quantum bit, the stored quantum bit is moved from the storage region to the operation region by a shuttle operation of moving the quantum bit with a Coulomb force generated by using the plurality of gate electrodes, and the quantum gate operation of changing the spin state to the quantum bit is performed in the operation region.

Abstract: One preferred aspect of the invention is a quantum computer of a semiconductor, including: a semiconductor crystalline substrate; a gate electrode array structure formed on a surface of the semiconductor crystalline substrate; and a reservoir unit that is a carrier supply unit, in which a classic potential barrier is formed in the semiconductor crystalline substrate by controlling an applied voltage to the gate electrode array structure, and a charge supplied from the reservoir unit is transported into the classic potential barrier.

Abstract: A quantum bit array comprises a semiconductor layer, an insulating layer arranged on the semiconductor layer, and a plurality of first gate electrodes which are arranged on the insulating layer. The plurality of first gate electrodes are each configured to trap an electron having a predetermined spin state in the semiconductor layer through application of a voltage. The quantum bit array comprises means for causing, in a case where the spin state of the electron is to be changed, a current for forming a magnetic field that acts on the electron to flow through at least one of the plurality of first gate electrodes in an extending direction of the at least one of the plurality of first gate electrodes.

Abstract: The first layer includes a first gate electrode array disposed in the first direction to control the qubits of the qubit string, and a second gate electrode array disposed in the first direction to control the inter-qubit interaction of the interaction string. The second layer includes a third gate electrode array disposed in the second direction, and a fourth gate electrode array disposed in the second direction adjacently to the third gate electrode array. The third and the fourth gate electrode arrays control a part of the multiple qubits, and a part of the multiple inter-qubit interactions, respectively.

Abstract: A semiconductor device includes an active region famed in a semiconductor layer formed on an insulating film famed in a semiconductor substrate and having a first extension portion extending in a first direction and a second extension portion extending in a second direction intersecting with the first direction, a first diffusion layer electrode of a first conductivity type provided in the first extension portion, second and third diffusion layer electrodes of a second conductivity type provided in the second extension portion so as to interpose a first connecting portion connecting the first extension portion and the second extension portion, a first gate electrode famed on the first extension portion between the first diffusion layer electrode and the first connecting portion through an insulating film famed on the semiconductor layer, and a second gate electrode famed on the first connecting portion through the insulating film famed on the semiconductor layer.

Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.

Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

Abstract: Abnormal generation of heat of a power MOSFET is detected to improve the reliability of a semiconductor device. As its means, in a power MOSFET having a drain electrode on the side of a back surface of a semiconductor substrate and a source pad on the side of a main surface of the semiconductor substrate, two gate pads electrically connected to a gate pad connected to a gate electrode of the power MOSFET are formed on the side of the main surface of the semiconductor substrate. Further, there is provided a voltmeter connected in parallel with each of two current paths which connect the two gate pads and a gate driver.

Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

Abstract: In a SiC power MISFET having a lateral surface of a trench formed in an upper surface of a SiC epitaxial substrate as a channel region, a silicon carbide semiconductor device having low resistance, high performance, and high reliability is realized. As a means therefor, a SiC power MISFET is formed as an island-shaped unit cell on an upper surface of an n-type SiC epitaxial substrate that is provided with a drain region on a bottom surface thereof, the SiC power MISFET including: an n-type current diffusion region that surrounds a p-type body layer contact region and an n-type source region in the indicated order in a plan view; a p-type body layer and an n-type JFET region; a trench that is formed on the body layer so as to span between the source region and the current diffusion region adjacent each other in a first direction and extends in the first direction; and a gate electrode embedded in the trench with a gate insulating film therebetween.

Abstract: A semiconductor device includes a memory cell which is configured of a FinFET having a split-gate type MONOS structure, the FinFET has a plurality of source regions formed in a plurality of fins, and the plurality of source regions are commonly connected by a source line contact. Further, the FinFET has a plurality of drain regions formed in the plurality of fins, the plurality of drain regions are commonly connected by a bit line contact, and the FinFET constitutes a memory cell of 1 bit.

Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

Abstract: A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract: A part of the semiconductor substrate is processed to form fins protruding from the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate including the fin FA, and an opening is formed in the interlayer insulating film. Next, a dummy pattern including the dummy material and the insulating film is formed in the opening in a self-aligned manner. Thereafter, the dummy pattern is replaced with a memory gate electrode, a control gate electrode, and the like.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract: In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.

Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, and an n-type third semiconductor region. A trench is formed having a gate electrode therein in which the bottom face of the trench contacts the p-type semiconductor region. A metal layer is electrically connected to the third semiconductor region, and a source electrode electrically connects the second semiconductor region and the metal layer to each other.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.