Abstract: Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme.

Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.

Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.

Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.

Abstract: Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.

Abstract: Various embodiments of the present invention are generally directed to an apparatus comprising a programmable power source which uses an array of resistive sense memory cells, such as but not limited to STRAM or RRAM cells, to provide a controlled power bias to a load, such as but not limited to a micro-oscillator. In some embodiments, the programmable power source incorporates an array of serially connected resistive sense memory cells. A selectively controllable power level is applied by the programmable power source to a load in relation to a control input which selectively programs at least selected ones of the memory cells to a selected resistance state.

Abstract: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer.

Abstract: Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

Abstract: Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme.

Abstract: A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.

Abstract: Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.

Abstract: Programmable metallization cells (PMC) that include a first electrode; a solid electrolyte layer including clusters of high ion conductive material dispersed in a low ion conductive material; and a second electrode, wherein either the first electrode or the second electrode is an active electrode, and wherein the solid electrolyte layer is disposed between the first electrode and the second electrode. Methods of forming them are also included herein.

Abstract: Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.

Abstract: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure.

Abstract: An apparatus that includes a magnetic structure including a reference layer; and a free layer; an exchange coupling spacer layer; and a stabilizing layer, wherein the exchange coupling spacer layer is between the magnetic structure and the stabilizing layer and exchange couples the free layer of the magnetic structure to the stabilizing layer.

Abstract: A magnetic sensor having adjustable electrical dimensions, such as electrical read width and electrical stripe height, is disclosed. The magnetic sensor includes a sensor stack with one or more bias electrodes positioned with respect to the sensor stack. The electrical width or electrical stripe height of the sensor stack is a function of a voltage applied to the bias electrodes. The electric field produced by the bias electrodes alters the electrical profile of the magnetoresistive device.

Abstract: A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.

Abstract: A magnetic element having a ferromagnetic pinned layer, a ferromagnetic free layer, a non-magnetic spacer layer therebetween, and a porous non-electrically conducting current confinement layer between the free layer and the pinned layer. The current confinement layer forms an interface either between the free layer and the non-magnetic spacer layer or the pinned layer and the non-magnetic spacer layer.

Abstract: Spin-transfer torque memory includes a composite free magnetic element, a reference magnetic element having a magnetization orientation that is pinned in a reference direction, and an electrically insulating and non-magnetic tunneling barrier layer separating the composite free magnetic element from the magnetic reference element. The free magnetic element includes a hard magnetic layer exchanged coupled to a soft magnetic layer. The composite free magnetic element has a magnetization orientation that can change direction due to spin-torque transfer when a write current passes through the spin-transfer torque memory unit.

Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.