Abstract: A method of processing a substrate that includes: selectively depositing a self-assembled monolayer (SAM) on a metal line of the substrate, the SAM being in contact with the metal line, a surface of the substrate further including a first dielectric material that surrounds the metal line; selectively depositing a second dielectric material over the first dielectric material; forming a dielectric layer by depositing a third dielectric material over the second dielectric material and the SAM; and patterning the dielectric layer

Abstract: A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.

Abstract: Dielectric films for semiconductor devices and methods of forming. A processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, for example zirconium oxide, hafnium oxide, or a laminate or mixture thereof.

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.

Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract: Methods of forming condensed first layer and semiconductor structures formed from the methods are provided. The methods include, for instance providing at least one layer disposed over a substrate structure of a semiconductor structure, wherein the substrate structure includes an upper silicon region; and performing at least one oxidation process of the semiconductor structure, the at least one oxidation process reducing a thickness of the upper region, wherein the performing facilitates diffusing to form a condensed layer over the substrate structure.

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract: The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Abstract: Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate with a first gate structure and a second gate structure and a shallow trench isolation region outside of the first and second gate structures, depositing a mask on the first gate structure, and depositing a protection layer on the shallow trench isolation region to embed a STI protective cap.

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract: The present disclosure provides a semiconductor device comprising a substrate, an undoped HfO2 layer formed over the substrate and a TiN layer formed on the HfO2 layer. Herein, the undoped HfO2 layer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfO2 layer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfO2 layer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfO2 layer.

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.