Abstract: A circuit and method for reducing noise in a memory circuit is disclosed. In one embodiment, the circuit includes an amplifier, a first transistor and a second transistor. The first transistor is capable of pulling up a first input port of the amplifier in response to a complement of the second memory signal. The second transistor is capable of pulling of a second input port of the amplifier in response to a complement of the first memory signal. In one embodiment, the method includes receiving a first memory signal at a first input port of an amplifier, receiving a second memory signal at a second input port of the amplifier, and pulling up the second input port in response to a complement of the first memory signal.

Abstract: A differential current switch logic (DCSL) system is provided which has an evaluation tree including a plurality of input terminals and a pair of complementary output nodes. The DCSL system also has an output network which establishes a pair of state outputs at a predetermined level during a precharge phase and establishes the state outputs at complementary levels in response to the evaluation tree output nodes during an evaluate phase. First and second NMOS transistors are connected in series between the DCVS output state network and the evaluation tree output nodes with their gates coupled to the state outputs to isolate the outputs from the evaluation tree following evaluation.

Abstract: A domino logic circuit includes a clocked precharge stage coupled to a positive voltage rail with the precharge stage having an input. An evaluation network adapted to receive at least one input is coupled between the precharge stage and a common voltage rail. A static CMOS stage is coupled to the positive voltage rail, and includes an input and an output, the input being coupled to a junction formed by the precharge stage and the evaluation network. A negative voltage rail is coupled to the static CMOS stage to precharge the output negative.