Abstract: An Equipment Front End Module (EFEM) having a Front Opening Unified Pod (FOUP) dock and a tool access port, includes a robotic wafer handling system configured to transfer silicon wafers between a FOUP coupled to the FOUP dock and a process tool positioned for access via the tool access port. An air curtain system inside the EFEM is positioned to produce an air curtain across the tool access port while the port is open, acting to isolate the interior of the EFEM from the tool environment, and prevent passage of airborne contaminants into the EFEM via the access port.

Abstract: A showerhead is configured to be mounted inside a processing chamber and provide a processing gas onto a semiconductor wafer inside the processing chamber. The showerhead includes a supply plenum, a faceplate, and an electrode plate assembly. The faceplate is disposed at a side of the supply plenum. The electrode plate assembly is disposed between a gas source and the supply plenum. The electrode plate assembly includes a first plate having a unitary construction and having a plurality of first gas holes, and a second plate having a unitary construction and having a plurality of second gas holes. The second plate is located between the first plate and the supply plenum and separated from the first plate. The plurality of second gas holes are partially overlapped but misaligned with the plurality of first gas holes. A semiconductor apparatus having the same and a semiconductor process are also provided.

Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.

Abstract: A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.

Abstract: A deposition device structure is provided. The deposition device structure includes a heater in a chamber. The deposition device structure also includes a shower head over the heater. The shower head includes holes extending from a top surface of the shower head to a bottom surface of the shower head. The bottom surface of the shower head faces the heater. The bottom surface of the shower head has a first section and a second section. The second section of the bottom surface is rougher than the first section of the bottom surface.

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.

Abstract: The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate layer over the first portion and the second portion of the protection layer. The method for forming a semiconductor structure further includes patterning the dummy gate layer to form a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer.

Abstract: A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.

Abstract: A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.

Abstract: A method of controlling a position of an adjustable nozzle includes depositing a film on a surface of a wafer. The method includes measuring a thickness profile of the surface of the wafer. The method includes comparing the measurement of the thickness profile with a reference value using a control unit. The method includes transmitting a control signal to the adjustable nozzle to alter the position of the adjustable nozzle based on the result of the comparison. The adjustable nozzle includes a base having a hollow center portion for conducting gas, the base configured for connection to a gas source. The adjust nozzle includes a tip coupled to the base and having an opening for conducting gas from the base to the exterior of the nozzle, wherein the base is configured for pivoting about a longitudinal axis of the base in response to the control signal.

Abstract: The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate layer over the first portion and the second portion of the protection layer. The method for forming a semiconductor structure further includes patterning the dummy gate layer to form a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer.

Abstract: A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.

Abstract: The description relates to an adjustable nozzle capable of pivoting about an axis of the nozzle and translating along the axis of the nozzle. A high density plasma chemical vapor deposition (HDP CVD) chamber houses a plurality of adjustable nozzles. A feedback control system includes a control unit coupled to the adjustable nozzle and the HDP CVD chamber to form a more uniform thickness profile of films deposited on a wafer in the HDP CVD chamber.

Abstract: A method for forming a semiconductor device structure and an apparatus for heating a semiconductor substrate are provided. The method includes spin coating a material layer over a semiconductor substrate. The method also includes heating the material layer by using a first heater above the semiconductor substrate and a second heater below the semiconductor substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The semiconductor device structure includes spacers over opposite sidewalls of the gate stack. The spacers and the gate stack surround a recess over the gate stack. The semiconductor device structure includes a first insulating layer over the gate stack and an inner wall of the recess. The semiconductor device structure includes a second insulating layer over the first insulating layer. Materials of the first insulating layer and the second insulating layer are different, and a first thickness of the first insulating layer is less than a second thickness of the second insulating layer.

Abstract: The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.

Abstract: A showerhead is configured to be mounted inside a processing chamber and provide a processing gas onto a semiconductor wafer inside the processing chamber. The showerhead includes a supply plenum, a faceplate, and an electrode plate assembly. The faceplate is disposed at a side of the supply plenum. The electrode plate assembly is disposed between a gas source and the supply plenum. The electrode plate assembly includes a first plate having a unitary construction and having a plurality of first gas holes, and a second plate having a unitary construction and having a plurality of second gas holes. The second plate is located between the first plate and the supply plenum and separated from the first plate. The plurality of second gas holes are partially overlapped but misaligned with the plurality of first gas holes. A semiconductor apparatus having the same and a semiconductor process are also provided.

Abstract: The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

Abstract: A coating apparatus for forming a coating film over a substrate includes a spin chuck for holding and rotating the substrate, a central coating nozzle over a central portion of the substrate, a plurality of first coating nozzles surrounding the central coating nozzle and spaced apart from the central coating nozzle by substantially a same first distance, and a plurality of second coating nozzles surrounding the central coating nozzle and spaced apart from the central coating nozzle by substantially a same second distance, wherein the second distance is greater than the first distance.