Abstract: Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.

Abstract: The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.

Abstract: The present disclosure describes an inner spacer structure for a semiconductor device and a method for forming the same. The method for forming the inner spacer structure in the semiconductor device can include forming a vertical structure over a substrate, forming a gate structure over a portion of the vertical structure, exposing sidewalls of the portion of the vertical structure, forming multiple spacers over the sidewalls of the portion of the vertical structure, and forming a void in each of the multiple spacers.

Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.

Abstract: Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.

Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes providing a workpiece comprising a first source/drain region in a first device region and a second source/drain region in a second device region, depositing a dielectric layer over the first source/drain region and the second source drain region, forming a first via opening in the dielectric layer to expose the first source/drain region and a second via opening in the dielectric layer to expose the second source/drain region, annealing the workpiece to form a first semiconductor oxide feature over the exposed first source/drain region and a second semiconductor oxide feature over the exposed second source/drain region, removing the first semiconductor oxide feature to expose the first source/drain region in the first via opening in dielectric layer, and selectively forming a first epitaxial feature over the exposed first source/drain region.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.

Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.

Abstract: A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.

Abstract: A contact structure of a semiconductor device is provided. The contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: An embodiment complimentary metal-oxide-semiconductor (CMOS) device and an embodiment method of forming the same are provided. The embodiment CMOS device includes an n-type metal-oxide-semiconductor (NMOS) having a titanium-containing layer interposed between a first metal contact and an NMOS source and a second metal contact and an NMOS drain and a p-type metal-oxide-semiconductor (PMOS) having a PMOS source and a PMOS drain, the PMOS source having a first titanium-containing region facing a third metal contact, the PMOS drain including a second titanium-containing region facing a fourth metal contact.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: An invention includes an apparatus for locating a data cable. The apparatus includes a first connector configured to connect to a first electronic device, and a second connector configured to connect to a second electronic device. The first connector and the second connector are configured to allow data transmission between the first connector and the second connector via the data cable, and each of the first connector and the second connector include a display device and is configured to generate a same identifier for display at the display device of each connector in order to locate the data cable.