Patents by Inventor Ding-Lung Chen

Ding-Lung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230178657
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: January 31, 2023
    Publication date: June 8, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11631771
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Publication number: 20220344492
    Abstract: A method of manufacturing a capacitor structure is provided, including the following steps. A substrate is provided. A first doped silicon material layer is formed on the substrate. A surface flattening process is performed on the first doped silicon material layer through a plasma treatment. An insulating material layer is formed on the first doped silicon material layer after the surface flattening process is performed. A second doped silicon material layer is formed on the insulating material layer. The first doped silicon material layer is patterned into a first electrode. The insulating material layer is patterned into an insulating layer. The second doped silicon material layer is patterned into a second electrode. The method of manufacturing the capacitor structure may be used to produce a capacitor with better reliability and may improve capacitance density.
    Type: Application
    Filed: May 13, 2021
    Publication date: October 27, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Xiang Li, Ding Lung Chen, Changda Yao
  • Patent number: 11377347
    Abstract: A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: July 5, 2022
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Xiang Li, Ding Lung Chen
  • Patent number: 11342465
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: January 3, 2021
    Date of Patent: May 24, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11239373
    Abstract: A semiconductor device includes a dielectric structure, a first source/drain electrode, a second source/drain electrode, an oxide semiconductor layer, a gate dielectric layer, and a first gate electrode. The first source/drain electrode is disposed in the dielectric structure. The oxide semiconductor layer is disposed on the first source/drain electrode in a vertical direction. The second source/drain electrode disposed on the oxide semiconductor layer in the vertical direction. The gate dielectric layer is disposed on the dielectric structure and surrounds the oxide semiconductor layer in a horizontal direction. The gate dielectric layer includes a first portion and a second portion. The first portion is elongated in the horizontal direction. The second portion is disposed on the first portion and elongated in the vertical direction. The first gate electrode is disposed on the first portion of the gate dielectric layer.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: February 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiang Li, Ding-Lung Chen
  • Publication number: 20210399133
    Abstract: A semiconductor device includes a dielectric structure, a first source/drain electrode, a second source/drain electrode, an oxide semiconductor layer, a gate dielectric layer, and a first gate electrode. The first source/drain electrode is disposed in the dielectric structure. The oxide semiconductor layer is disposed on the first source/drain electrode in a vertical direction. The second source/drain electrode disposed on the oxide semiconductor layer in the vertical direction. The gate dielectric layer is disposed on the dielectric structure and surrounds the oxide semiconductor layer in a horizontal direction. The gate dielectric layer includes a first portion and a second portion. The first portion is elongated in the horizontal direction. The second portion is disposed on the first portion and elongated in the vertical direction. The first gate electrode is disposed on the first portion of the gate dielectric layer.
    Type: Application
    Filed: July 30, 2020
    Publication date: December 23, 2021
    Inventors: Xiang Li, Ding-Lung Chen
  • Publication number: 20210354983
    Abstract: A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.
    Type: Application
    Filed: July 1, 2020
    Publication date: November 18, 2021
    Inventors: Xiang Li, Ding Lung Chen
  • Publication number: 20210336059
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11088285
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: August 10, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11011649
    Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chen-Bin Lin, Ding-Lung Chen, Chi-Fa Ku
  • Publication number: 20210126131
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: January 3, 2021
    Publication date: April 29, 2021
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 10727234
    Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.
    Type: Grant
    Filed: November 27, 2016
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen, Xing Hua Zhang, Shan Liu, Runshun Wang, Chien-Fu Chen, Wei-Jen Wang, Chen-Hsien Hsu
  • Publication number: 20200083380
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: October 8, 2018
    Publication date: March 12, 2020
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 10446473
    Abstract: A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device includes a substrate, an interconnection structure, an oxide semiconductor (OS) transistor and a contact structure. The substrate has a first surface and a second surface opposite to the first surface. The interconnection structure is disposed on the first surface, and the oxide semiconductor (OS) transistor is disposed on the second surface. Also, the OS transistor includes a back gate disposed on the second surface of the substrate. The contact structure is formed between the OS transistor and the interconnection structure, and the contact structure is electrically connected to the back gate. The contact structure penetrates through the substrate for electrically connecting the interconnection structure to the OS transistor.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiang Li, Ding-Lung Chen, En-Feng Liu, Yu-Cheng Tung
  • Patent number: 10355019
    Abstract: A semiconductor device includes a substrate, a first transistor, a first diode structure, and a second diode structure. The first transistor is disposed on the substrate. The first transistor includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the substrate by the first diode structure. The first drain electrode is connected to the substrate by the second diode structure. The first diode structure and the second diode structure may be used to improve potential unbalance in the transistor, and operation performance and reliability of the semiconductor device may be enhanced accordingly.
    Type: Grant
    Filed: July 1, 2018
    Date of Patent: July 16, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiang Li, Ding-Lung Chen, Yu-Cheng Tung
  • Patent number: 10276476
    Abstract: A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device includes a substrate, an interconnection structure, an oxide semiconductor (OS) transistor and a contact structure. The substrate has a first surface and a second surface opposite to the first surface. The interconnection structure is disposed on the first surface, and the oxide semiconductor (OS) transistor is disposed on the second surface. Also, the OS transistor includes a back gate disposed on the second surface of the substrate. The contact structure is formed between the OS transistor and the interconnection structure, and the contact structure is electrically connected to the back gate. The contact structure penetrates through the substrate for electrically connecting the interconnection structure to the OS transistor.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiang Li, Ding-Lung Chen, En-Feng Liu, Yu-Cheng Tung
  • Publication number: 20180331233
    Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 15, 2018
    Inventors: ZHIBIAO ZHOU, Shao-Hui Wu, Chen-Bin Lin, Ding-Lung Chen, Chi-Fa Ku
  • Patent number: 10056493
    Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: August 21, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen, Chen-Bin Lin, Sanpo Wang, Chung-Yuan Lee, Chi-Fa Ku
  • Patent number: 10043917
    Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Shao-Hui Wu, Chen-Bin Lin, Ding-Lung Chen, Chi-Fa Ku