Patents by Inventor Ding Ming

Ding Ming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8217521
    Abstract: A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: July 10, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Ting-Sheng Chen, Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20120146207
    Abstract: A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip.
    Type: Application
    Filed: January 7, 2011
    Publication date: June 14, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Patent number: 8193006
    Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: June 5, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20120133807
    Abstract: An image capture apparatus comprises an image sensor array including a plurality of image sensors arranged in a two-dimensional (2-D) array and an analog-to-digital converter (ADC) array including a plurality of ADCs arranged in a 2-D array. The image sensor array is divided into a plurality of sub-arrays, each of which includes at least two image sensors. The image sensor array is vertically stacked on the ADC array. Each ADC corresponds to one sub-array of image sensors and is coupled to process signals output by the image sensors in the corresponding sub-array.
    Type: Application
    Filed: December 23, 2010
    Publication date: May 31, 2012
    Inventors: Cheng-Wen Wu, Ding-Ming Kwai, Jim Li, Ka-Yi Yeh
  • Patent number: 8133475
    Abstract: The present invention relates to chewing gum and confectionery compositions for improving the dental health of mammals, particularly humans. In particular, the compositions may include a gum base or carrier, sweetening agents, casein phosphopeptide-calcium phosphate (CPP-ACP) and food-grade acids. The compositions may be employed to remineralize the tooth surfaces of mammals, as well as impart acid resistance thereto.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: March 13, 2012
    Assignee: Cadbury Adams USA, LLC
    Inventors: Doris Tancredi, Ding Ming, Samantha Holme
  • Publication number: 20110304010
    Abstract: An electrostatic discharge (ESD) protection scheme for a semiconductor device stacking process is provided, in which an equivalent electrical resistance of a specific path is designed to be less than an equivalent electrical resistance of other paths. Accordingly, when a first active layer and a second active layer in the semiconductor device are stacked, by designing suitable ESD protection cells on such a specific path, electrical charges accumulated on the top layer wafer (or die) select such a specific path over the other paths to be released to the grounded bottom layer wafer (or die), so as to achieve an ESD protection effect. In addition, since such a specific path also serves as a heat dissipation path in a three dimensional integrated circuit (3D IC), an overall heat resistance of the 3D IC may be reduced to improve a heat dissipation effect.
    Type: Application
    Filed: August 5, 2010
    Publication date: December 15, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Zhe-Wei Jiang, Ding-Ming Kwai, Shih-Hung Chen
  • Patent number: 8026585
    Abstract: A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: September 27, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Patent number: 7924083
    Abstract: An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: April 12, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20110080185
    Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.
    Type: Application
    Filed: May 6, 2010
    Publication date: April 7, 2011
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHENG WEN WU, PO YUAN CHEN, DING MING KWAI, YUNG FA CHOU
  • Publication number: 20110080184
    Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 7, 2011
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHENG WEN WU, PO YUAN CHEN, DING MING KWAI, YUNG FA CHOU
  • Publication number: 20110006829
    Abstract: An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.
    Type: Application
    Filed: August 31, 2009
    Publication date: January 13, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20100320565
    Abstract: A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV.
    Type: Application
    Filed: September 24, 2009
    Publication date: December 23, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ting-Sheng Chen, Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20100297203
    Abstract: The present invention relates to chewing gum and confectionery compositions and methods for reducing dental caries in mammals. In particular, the compositions may include a gum base or carrier, sweetening agents and casein phosphopeptide-calcium phosphate (CPP-ACP). The compositions may be employed to slow the progression and enhance the regression of carious lesions in mammals, particularly in humans.
    Type: Application
    Filed: August 5, 2010
    Publication date: November 25, 2010
    Applicant: CADBURY ADAMS USA, LLC
    Inventors: Doris Tancredi, Ding Ming, Jack W. Vincent
  • Publication number: 20100295189
    Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.
    Type: Application
    Filed: August 6, 2009
    Publication date: November 25, 2010
    Applicant: Industrial Technology Research Institute
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20100289139
    Abstract: A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.
    Type: Application
    Filed: September 24, 2009
    Publication date: November 18, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ting-Sheng Chen, Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20100244220
    Abstract: A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.
    Type: Application
    Filed: June 15, 2009
    Publication date: September 30, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yung-Fa Chou, Ding-Ming Kwai
  • Publication number: 20070237856
    Abstract: The present invention relates to chewing gum and confectionery compositions and methods for reducing dental caries in mammals. In particular, the compositions may include a gum base or carrier, sweetening agents and casein phosphopeptide-calcium phosphate (CPP-ACP). The compositions may be employed to slow the progression and enhance the regression of carious lesions in mammals, particularly in humans.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 11, 2007
    Inventors: Doris Tancredi, Ding Ming, Jack W. Vincent
  • Publication number: 20070237804
    Abstract: The present invention relates to chewing gum and confectionery compositions and methods for reducing dental caries in mammals. In particular, the compositions may include a gum base or carrier, sweetening agents and casein phosphopeptide-calcium phosphate (CPP-ACP). The compositions may be employed to slow the progression and enhance the regression of carious lesions in mammals, particularly in humans.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 11, 2007
    Inventors: Doris Tancredi, Ding Ming, Jack W. Vincent
  • Publication number: 20070237805
    Abstract: The present invention relates to chewing gum and confectionery compositions for improving the dental health of mammals, particularly humans. In particular, the compositions may include a gum base or carrier, sweetening agents, casein phosphopeptide-calcium phosphate (CPP-ACP) and food-grade acids. The compositions may be employed to remineralize the tooth surfaces of mammals, as well as impart acid resistance thereto.
    Type: Application
    Filed: April 4, 2007
    Publication date: October 11, 2007
    Inventors: Doris Tancredi, Ding Ming, Samantha Holme
  • Patent number: RE40594
    Abstract: The present invention relates to methods for identifying inhibitors of the bitter taste response, and by methods of using such inhibitors to either block the perception of bitterness and/or promote the perception of a sweet taste. The inhibitors of the invention may be used as flavor enhancers in foods and pharmaceuticals. The methods of the invention may further be used to characterize the gustatory perception of novel tastants.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: December 2, 2008
    Assignee: Mount Sinai School of Medicine of New York University
    Inventors: Robert F. Margolskee, Ding Ming