Patents by Inventor Dipankar Das

Dipankar Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180293492
    Abstract: One embodiment provides for a non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising providing an interface to define a neural network using machine-learning domain specific terminology, wherein the interface enables selection of a neural network topology and abstracts low-level communication details of distributed training of the neural network.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Dhiraj D. Kalamkar, KARTHIKEYAN VAIDYANATHAN, SRINIVAS SRIDHARAN, DIPANKAR DAS
  • Publication number: 20180293493
    Abstract: One embodiment provides for a method of transmitting data between multiple compute nodes of a distributed compute system, the method comprising creating a global view of communication operations to be performed between the multiple compute nodes of the distributed compute system, the global view created using information specific to a machine learning model associated with the distributed compute system; using the global view to determine a communication cost of the communication operations; and automatically determining a number of network endpoints for use in transmitting the data between the multiple compute nodes of the distributed compute system.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Dhiraj D. Kalamkar, KARTHIKEYAN VAIDYANATHAN, SRINIVAS SRIDHARAN, DIPANKAR DAS
  • Publication number: 20180285733
    Abstract: Technologies for artificial neural network training include a computing node with a host fabric interface that sends a message that includes one or more artificial neural network training algorithm values to another computing node in response to receipt of a request to send the message. Prior to sending the message, the host fabric interface may receive a request to quantize the message and quantize the message based on a quantization level included in the request to generate a quantized message. The quantization message includes one or more quantized values such that each quantized value has a lower precision than a corresponding artificial neural network training algorithm value. The host fabric interface then transmits the quantized message, which includes metadata indicative of the quantization level, to another computing node in response to quantization of the message for artificial neural network training. Other embodiments are described and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Naveen K. Mellempudi, Srinivas Sridharan, Dheevatsa Mudigere, Dipankar Das
  • Publication number: 20180251678
    Abstract: The present invention relates to a process for the preparation of blue-fluorescence emitting carbon dots (CDTs) from sub-bituminous tertiary high sulfur Indian coals. More particularly, the present invention relates to the production of characteristics carbon dots from low-quality Indian coals by an ultrasonic-assisted wet-chemical method. Also, the present invention provides a simple and environmentally benign method for fabrication of characteristics and size-controlled carbon dots.
    Type: Application
    Filed: September 14, 2017
    Publication date: September 6, 2018
    Inventors: Binoy Kumar SAIKIA, Tonkeswar DAS, Sonali ROY, Bardwi NARZARY, Hari Prasanna DEKABORUAH, Manobjyoti BORDOLOI, Jiumoni LAHKAR, Dipankar NEOG, Danaboyina RAMAIAH
  • Publication number: 20180045569
    Abstract: A spectral imaging system includes a spectrometer and an optics imaging system. The spectrometer is operable for generating spectral signatures of objects from a scene. The optics imaging system is operable to generate six or more responses from the same scene. Each of the six or more responses represents different spectral content of the objects in the scene. The responses generated by the optics imaging system can be used to generate a hypercube using spectral reconstruction techniques. In an embodiment, the spectral imaging system could be implemented as part of a mobile phone.
    Type: Application
    Filed: August 14, 2017
    Publication date: February 15, 2018
    Applicant: SPECTRAL INSIGHTS PRIVATE LIMITED
    Inventors: Sumit Nath, Dipankar Das, Suhash Gerald
  • Patent number: 9594129
    Abstract: The present invention discloses highly sensitive magnetic heterojunction device consisting of a composite comprising ferromagnetic (La0.66Sr0.34MnO3) LSMO layer with ultra-thin ferrimagnetic CoFe2O4 (CFO) layer capable of giant resistive switching (RS) which can be tuned at micro tesla magnetic field at room temperature.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: March 14, 2017
    Assignee: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Satishchandra Balkrishna Ogale, Dipankar Das Sarma, Abhimanyu Singh Rana, Vishal Prabhakar Thakare, Anil Kumar Puri
  • Patent number: 9430677
    Abstract: Methods and systems are provided for managing static memory associated with software of an embedded system. The method includes performing one or more steps on one or more processors. The steps include selectively assigning memory objects to static memory segments based on access of the memory object by the software; managing data of the memory segments based on the assigning; and selectively restoring the data of the memory segments based on the managing.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 30, 2016
    Assignee: GM GLOBLA TECHNOLOGY OPERATIONS LLC
    Inventor: Dipankar Das
  • Patent number: 8930036
    Abstract: An electrical network architecture including a reconfigurable interface layer, along with a corresponding reconfiguration methodology. The interface layer is comprised of reconfigurable interface devices which allow a plurality of sensors and actuators to communicate with a plurality of control units. Each sensor or actuator is connected to multiple interface devices, which in turn are connected to a bus. The control units are also connected to the bus. In the event of an interface device failure, other interface devices can be reconfigured to maintain communication between sensors, actuators and control units. In the event of a control unit failure, the interface devices can be reconfigured to route sensor and actuator message traffic to a different control unit which can handle the functions of the failed control unit. The overall number of control units can also be reduced, as each control unit has flexible access to many sensors and actuators.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: January 6, 2015
    Assignee: GM Global Technology Operations LLC
    Inventors: Dipankar Das, Vinod Kumar Agrawal, Seetharaman Rajappan
  • Publication number: 20140287534
    Abstract: The present invention discloses highly sensitive magnetic heterojunction device consisting of a composite comprising ferromagnetic (La0.66Sr0.34MnO3) LSMO layer with ultra-thin ferrimagnetic CoFe2O4 (CFO) layer capable of giant resistive switching (RS) which can be tuned at micro tesla magnetic field at room temperature.
    Type: Application
    Filed: June 25, 2012
    Publication date: September 25, 2014
    Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Satishchandra Balkrishna Ogale, Dipankar Das Sarma, Abhimanyu Singh Rana, Vishal Prabhakar Thakare, Anil Kumar Puri
  • Patent number: 8806282
    Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: August 12, 2014
    Assignee: LSI Corporation
    Inventors: Varun Shetty, Debjit Roy Choudhury, Dipankar Das, Ashank Reddy
  • Patent number: 8677189
    Abstract: A method and system for recovering from stack-overflow or stack-underflow faults without restarting software or hardware. At every task switch operation in an application program, a portion of the memory stack is copied to a backup location, so that portion of the stack can be restored if it is subsequently corrupted by a stack-overflow or stack-underflow fault during the execution of the next task. State variable data is similarly copied to a backup location, so that it can be used to restore or estimate the output of the next task if that task experiences a fault. Techniques are disclosed for selecting which state variable data and which portion of the memory stack to copy to backup, and for detecting a stack-overflow or stack-underflow fault and restoring state variable and memory data in the event of such a fault.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: March 18, 2014
    Assignee: GM Global Technology Operations LLC
    Inventor: Dipankar Das
  • Publication number: 20140058532
    Abstract: A system and method for compartmentalizing memory sections in a controller to allow compartments to be individually reprogrammed without affecting files in other compartments. The method includes defining a main memory in the controller that stores a plurality of different types of content files that each include lines of code, where the main memory includes compartments having memory slots for lines of code that have been programmed and empty memory slots where lines of codes can be written into. The main memory is initially programmed to store desired content files in the memory compartments. Subsequently, if it is determined that code stored in the main memory needs to be reprogrammed, the reprogramming is performed to flash only the memory compartments that include the code that needs to be reprogrammed and those memory compartments that include code that is linked to the code that needs to be reprogrammed.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: DIPANKAR DAS, SEETHARAMAN RAJAPPAN, SRINATH S., KIRAN H. K.
  • Publication number: 20140019668
    Abstract: Methods and systems are provided for managing static memory associated with software of an embedded system. The method includes performing one or more steps on one or more processors. The steps include selectively assigning memory objects to static memory segments based on access of the memory object by the software; managing data of the memory segments based on the assigning; and selectively restoring the data of the memory segments based on the managing.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventor: Dipankar DAS
  • Publication number: 20130318322
    Abstract: A memory management apparatus includes a first controller adapted to receive an input data sequence including one or more data frames and operative: to separate each of the data frames into a payload data portion and a header portion; to store the payload data portion in at least one available memory location in a physical storage space; and to store in a logical storage space the header portion along with at least one associated index indicating where in the physical storage space the corresponding payload data portion resides. The apparatus further includes a second controller operative, as a function of a data read request, to access the physical storage space using the header portion and associated index from the logical storage space to retrieve the corresponding payload data portion and to combine the header portion with the payload data portion to generate a response to the data read request.
    Type: Application
    Filed: May 28, 2012
    Publication date: November 28, 2013
    Applicant: LSI CORPORATION
    Inventors: Varun Shetty, Dipankar Das, Debjit Roy Choudhury, Ashank Reddy
  • Publication number: 20130219234
    Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: LSI CORPORATION
    Inventors: Varun Shetty, Debjit Roy Choudhury, Dipankar Das, Ashank Reddy
  • Patent number: 8464102
    Abstract: A transportation vehicle including a high-resolution clock, an electronic network including two or more tasks, including first and second tasks, and a memory including instructions causing a processor to classify faults in the electronic network using the clock. The steps include receiving a first fault code generated at the first task, receiving a second fault trouble code generated at the second task of the electronic system in response to a second fault, and identifying an execution cycle offset associated with the first and second tasks using an execution schedule, and considering whether the first cycle is separated from the second cycle by the execution cycle offset identified by the schedule. The instructions also cause the processor to identify causal relationships for a plurality of faults via a pair-wise repetition of the above-described analysis for at least one combination of tasks other than the first and second tasks.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: June 11, 2013
    Assignee: GM Global Technology Operations LLC
    Inventors: Purnendu Sinha, Dipankar Das
  • Publication number: 20130124917
    Abstract: A method and system for recovering from stack-overflow or stack-underflow faults without restarting software or hardware. At every task switch operation in an application program, a portion of the memory stack is copied to a backup location, so that portion of the stack can be restored if it is subsequently corrupted by a stack-overflow or stack-underflow fault during the execution of the next task. State variable data is similarly copied to a backup location, so that it can be used to restore or estimate the output of the next task if that task experiences a fault. Techniques are disclosed for selecting which state variable data and which portion of the memory stack to copy to backup, and for detecting a stack-overflow or stack-underflow fault and restoring state variable and memory data in the event of such a fault.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventor: Dipankar Das
  • Publication number: 20130002842
    Abstract: Systems and methods for extracting and measuring motion from images capture during capsule endoscopy in accordance with embodiments of the invention are disclosed. In one embodiment of the invention, an endoscope system configured to generate a spatial index of images captured along a passageway includes a processor and a camera configured to capture a plurality of images as the camera moves along a passageway, wherein the processor is configured to compare sets of at least two images from the plurality of images, determine motion of the camera along the passageway using the sets of at least two images, determine the distance the camera traveled along the passageway at the point at which an image in each of the sets of at least two images was captured, and generate a spatial index for the plurality of images by associating distances traveled along the passageway with the images.
    Type: Application
    Filed: April 26, 2012
    Publication date: January 3, 2013
    Applicant: Ikona Medical Corporation
    Inventors: Dipankar Das, Marcus O. Filipovich, Jason J. Corso, Gregory D. Hager
  • Publication number: 20120265359
    Abstract: An electrical network architecture including a reconfigurable interface layer, along with a corresponding reconfiguration methodology. The interface layer is comprised of reconfigurable interface devices which allow a plurality of sensors and actuators to communicate with a plurality of control units. Each sensor or actuator is connected to multiple interface devices, which in turn are connected to a bus. The control units are also connected to the bus. In the event of an interface device failure, other interface devices can be reconfigured to maintain communication between sensors, actuators and control units. In the event of a control unit failure, the interface devices can be reconfigured to route sensor and actuator message traffic to a different control unit which can handle the functions of the failed control unit. The overall number of control units can also be reduced, as each control unit has flexible access to many sensors and actuators.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Dipankar DAS, Vinod Kumar AGRAWAL, Seetharaman RAJAPPAN
  • Publication number: 20120166878
    Abstract: A transportation vehicle including a high-resolution clock, an electronic network including two or more tasks, including first and second tasks, and a memory including instructions causing a processor to classify faults in the electronic network using the clock. The steps include receiving a first fault code generated at the first task, receiving a second fault trouble code generated at the second task of the electronic system in response to a second fault, and identifying an execution cycle offset associated with the first and second tasks using an execution schedule, and considering whether the first cycle is separated from the second cycle by the execution cycle offset identified by the schedule. The instructions also cause the processor to identify causal relationships for a plurality of faults via a pair-wise repetition of the above-described analysis for at least one combination of tasks other than the first and second tasks.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, LLC
    Inventors: Purnendu Sinha, Dipankar Das