Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a fetch unit to fetch a single instruction having multiple input operands, wherein the multiple input operands have an unequal bit-length, a first input operand having a first bit-length and a second input operand having a second bit-length; a decode unit to decode the single instruction into a decoded instruction; an operand length unit to determine a smaller bit-length of the first bit-length and the second bit-length; and a compute unit to perform a matrix operation on the multiple input operands to generate an output value having a bit length of the smaller bit length.

Abstract: One embodiment provides for a system to compute and distribute data for distributed training of a neural network, the system including first memory to store a first set of instructions including a machine learning framework; a fabric interface to enable transmission and receipt of data associated with the set of trainable machine learning parameters; a first set of general-purpose processor cores to execute the first set of instructions, the first set of instructions to provide a training workflow for computation of gradients for the trainable machine learning parameters and to communicate with a second set of instructions, the second set of instructions facilitate transmission and receipt of the gradients via the fabric interface; and a graphics processor to perform compute operations associated with the training workflow to generate the gradients for the trainable machine learning parameters.

Abstract: One embodiment provides for a machine-learning accelerator device a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream. The compute unit includes compute logic configured to execute a single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the compute logic to scale the input tensor to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type.

Abstract: One embodiment provides for a computing device comprising a parallel processor compute unit to perform a set of parallel integer compute operations; a ternarization unit including a weight ternarization circuit and an activation quantization circuit; wherein the weight ternarization circuit is to convert a weight tensor from a floating-point representation to a ternary representation including a ternary weight and a scale factor; wherein the activation quantization circuit is to convert an activation tensor from a floating-point representation to an integer representation; and wherein the parallel processor compute unit includes one or more circuits to perform the set of parallel integer compute operations on the ternary representation of the weight tensor and the integer representation of the activation tensor.

Abstract: One embodiment provides for a non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising providing an interface to define a neural network using machine-learning domain specific terminology, wherein the interface enables selection of a neural network topology and abstracts low-level communication details of distributed training of the neural network.

Abstract: One embodiment provides for a method of transmitting data between multiple compute nodes of a distributed compute system, the method comprising creating a global view of communication operations to be performed between the multiple compute nodes of the distributed compute system, the global view created using information specific to a machine learning model associated with the distributed compute system; using the global view to determine a communication cost of the communication operations; and automatically determining a number of network endpoints for use in transmitting the data between the multiple compute nodes of the distributed compute system.

Abstract: Technologies for artificial neural network training include a computing node with a host fabric interface that sends a message that includes one or more artificial neural network training algorithm values to another computing node in response to receipt of a request to send the message. Prior to sending the message, the host fabric interface may receive a request to quantize the message and quantize the message based on a quantization level included in the request to generate a quantized message. The quantization message includes one or more quantized values such that each quantized value has a lower precision than a corresponding artificial neural network training algorithm value. The host fabric interface then transmits the quantized message, which includes metadata indicative of the quantization level, to another computing node in response to quantization of the message for artificial neural network training. Other embodiments are described and claimed.

Abstract: A spectral imaging system includes a spectrometer and an optics imaging system. The spectrometer is operable for generating spectral signatures of objects from a scene. The optics imaging system is operable to generate six or more responses from the same scene. Each of the six or more responses represents different spectral content of the objects in the scene. The responses generated by the optics imaging system can be used to generate a hypercube using spectral reconstruction techniques. In an embodiment, the spectral imaging system could be implemented as part of a mobile phone.

Abstract: The present invention discloses highly sensitive magnetic heterojunction device consisting of a composite comprising ferromagnetic (La0.66Sr0.34MnO3) LSMO layer with ultra-thin ferrimagnetic CoFe2O4 (CFO) layer capable of giant resistive switching (RS) which can be tuned at micro tesla magnetic field at room temperature.

Abstract: Methods and systems are provided for managing static memory associated with software of an embedded system. The method includes performing one or more steps on one or more processors. The steps include selectively assigning memory objects to static memory segments based on access of the memory object by the software; managing data of the memory segments based on the assigning; and selectively restoring the data of the memory segments based on the managing.

Abstract: An electrical network architecture including a reconfigurable interface layer, along with a corresponding reconfiguration methodology. The interface layer is comprised of reconfigurable interface devices which allow a plurality of sensors and actuators to communicate with a plurality of control units. Each sensor or actuator is connected to multiple interface devices, which in turn are connected to a bus. The control units are also connected to the bus. In the event of an interface device failure, other interface devices can be reconfigured to maintain communication between sensors, actuators and control units. In the event of a control unit failure, the interface devices can be reconfigured to route sensor and actuator message traffic to a different control unit which can handle the functions of the failed control unit. The overall number of control units can also be reduced, as each control unit has flexible access to many sensors and actuators.

Abstract: The present invention discloses highly sensitive magnetic heterojunction device consisting of a composite comprising ferromagnetic (La0.66Sr0.34MnO3) LSMO layer with ultra-thin ferrimagnetic CoFe2O4 (CFO) layer capable of giant resistive switching (RS) which can be tuned at micro tesla magnetic field at room temperature.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: A method and system for recovering from stack-overflow or stack-underflow faults without restarting software or hardware. At every task switch operation in an application program, a portion of the memory stack is copied to a backup location, so that portion of the stack can be restored if it is subsequently corrupted by a stack-overflow or stack-underflow fault during the execution of the next task. State variable data is similarly copied to a backup location, so that it can be used to restore or estimate the output of the next task if that task experiences a fault. Techniques are disclosed for selecting which state variable data and which portion of the memory stack to copy to backup, and for detecting a stack-overflow or stack-underflow fault and restoring state variable and memory data in the event of such a fault.

Abstract: A system and method for compartmentalizing memory sections in a controller to allow compartments to be individually reprogrammed without affecting files in other compartments. The method includes defining a main memory in the controller that stores a plurality of different types of content files that each include lines of code, where the main memory includes compartments having memory slots for lines of code that have been programmed and empty memory slots where lines of codes can be written into. The main memory is initially programmed to store desired content files in the memory compartments. Subsequently, if it is determined that code stored in the main memory needs to be reprogrammed, the reprogramming is performed to flash only the memory compartments that include the code that needs to be reprogrammed and those memory compartments that include code that is linked to the code that needs to be reprogrammed.

Abstract: Methods and systems are provided for managing static memory associated with software of an embedded system. The method includes performing one or more steps on one or more processors. The steps include selectively assigning memory objects to static memory segments based on access of the memory object by the software; managing data of the memory segments based on the assigning; and selectively restoring the data of the memory segments based on the managing.

Abstract: A memory management apparatus includes a first controller adapted to receive an input data sequence including one or more data frames and operative: to separate each of the data frames into a payload data portion and a header portion; to store the payload data portion in at least one available memory location in a physical storage space; and to store in a logical storage space the header portion along with at least one associated index indicating where in the physical storage space the corresponding payload data portion resides. The apparatus further includes a second controller operative, as a function of a data read request, to access the physical storage space using the header portion and associated index from the logical storage space to retrieve the corresponding payload data portion and to combine the header portion with the payload data portion to generate a response to the data read request.

Abstract: An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data processing system for transferring at least one data block therebetween. The data processing system further includes an error detection module associated with the controller. The error detection module is operative to determine a probability of an error occurrence based at least in part on a measured current error rate for the data processing system. The controller is operative to implement an error correction methodology which is selectively adaptable as a function of the probability of an error occurrence.

Abstract: A transportation vehicle including a high-resolution clock, an electronic network including two or more tasks, including first and second tasks, and a memory including instructions causing a processor to classify faults in the electronic network using the clock. The steps include receiving a first fault code generated at the first task, receiving a second fault trouble code generated at the second task of the electronic system in response to a second fault, and identifying an execution cycle offset associated with the first and second tasks using an execution schedule, and considering whether the first cycle is separated from the second cycle by the execution cycle offset identified by the schedule. The instructions also cause the processor to identify causal relationships for a plurality of faults via a pair-wise repetition of the above-described analysis for at least one combination of tasks other than the first and second tasks.

Abstract: A method and system for recovering from stack-overflow or stack-underflow faults without restarting software or hardware. At every task switch operation in an application program, a portion of the memory stack is copied to a backup location, so that portion of the stack can be restored if it is subsequently corrupted by a stack-overflow or stack-underflow fault during the execution of the next task. State variable data is similarly copied to a backup location, so that it can be used to restore or estimate the output of the next task if that task experiences a fault. Techniques are disclosed for selecting which state variable data and which portion of the memory stack to copy to backup, and for detecting a stack-overflow or stack-underflow fault and restoring state variable and memory data in the event of such a fault.