Abstract: Methods and systems for barcode enabled virtual coupon search, retrieval, presentation, and redemption via telecommunications devices. One system includes using a mobile phone camera to scan product barcodes. The system further includes an Internet connected coupon server that, in response to user queries via mobile phone camera scans of product barcodes, retrieves and displays on mobile phone product-specific primary and competing product secondary coupon images for user selection. In response to mobile phone user selection of desired coupons, the system stores in a pending file on coupon server, product-specific primary and competing product secondary coupons, in the form of a coupon issuer reloadable and scalable stored coupon value with an escrow account or merchant bank account number, for matching bar code search request.

Abstract: A system for batch forming a sheet of spring elements in three dimensions is described. A spring element sheet containing spring elements defined in two dimensions is arranged between two mating die press plates. A force is applied to the mating die press plates to form the two-dimensional spring contact elements into three dimensions. Alternatively, configurable die press plates are used to selectively form a two-dimensional spring element sheet into three-dimensional spring contacts.

Abstract: An elastic contact array circuitized substrate includes a circuitized substrate provided with circuit traces, and an array of three dimensional contact elements joined to the circuitized substrate and electrically coupled to the circuit traces. In one configuration, the array of three dimensional contacts are formed in a spring sheet material having anisotropic grains whose long direction is selected with respect to the longitudinal direction of elastic contact arms, in accordance with desired properties. In another configuration of the invention, the circuit traces are formed integrally within the spring sheet material.

Abstract: A contact of a connector element arranged in an array of connector elements having desirable mechanical and electrical properties simultaneously, as defined by a robust working range. An array pitch is preferably within a range of about 0.05 mm to about 1.27 mm, and preferably within a range of about 0.05 mm to 1 mm. The contact includes a base portion and an elastically deformable portion that protrudes from a plane containing the base and is configured to provide a working range of about 0.0 mm to about 1.0 mm.

Abstract: A connector for electrically connecting to pads formed on a semiconductor device includes a substrate and an array of contact elements of conductive material formed on the substrate. Each contact element includes a base portion attached to the top surface of the substrate and a curved spring portion extending from the base portion and having a distal end projecting above the substrate. The curved spring portion is formed to curve away from a plane of contact and has a curvature disposed to provide a controlled wiping action when engaging a respective pad of the semiconductor device.

Abstract: A method for forming a connector including an array of contact elements includes forming a support layer on a substrate, patterning the support layer to define an array of support elements, isotropically etching the support elements to form rounded corners on the top of each support element, forming and patterning a metal layer to define an array of contact elements where each contact element includes a first metal portion on the substrate and a second metal portion extending from the first metal portion and partially across the top of a respective support element, and removing the support elements. The contact elements thus formed each includes a base portion attached to the substrate and a curved spring portion extending from the base portion and having a distal end projecting above the substrate. The curved spring portion is formed to have a concave curvature with respect to the surface of the substrate.

Abstract: A self-aligned semiconductor interconnect barrier between channels and vias is provided which is self-aligned and made of a metallic barrier material. A channel is conventionally formed in the semiconductor dielectric, lined with a first metallic barrier material, and filled with a conductive material. A recess is etched to a predetermined depth into the conductive material, and the second metallic barrier material is deposited and removed outside the channel. This leaves the conductive material totally enclosed in metallic barrier material. The metallic barrier material is selected from metals such as tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof.

Abstract: A semiconductor metalization barrier, and manufacturing method therefor, is provided which is a stack of a cobalt layer and cobalt tungsten layer deposited on a copper bonding pad.

Abstract: A method is provided for forming seed layers in a channel or via by applying a high bias to the material of the seed layer during deposition. This sputters off the seed layer overhang in order to reduce the electrical resistance of the seed layer, maintain its barrier effectiveness and enhance the subsequent filling of the channel or via by conductive materials.

Abstract: A method for manufacturing an integrated circuit using damascene processes is provided in which dielectric surfaces subject to chemical-mechanical polishing are roughened after polishing to increase the surface area to provide more surface for chemical and mechanical bonding of subsequent layers.

Abstract: An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.

Abstract: A method is provided for forming seed layers in semiconductor device channels or vias by using an inert gas sputter etching technique. The technique etches back the seed layers which results in a reduction of seed layer overhang at the top of the channels or vias, thereby enhancing the subsequent filling of the channel or vias by conductive materials.

Abstract: A method is provided for forming seed layers in semiconductor channel and via openings by using a two-stage approach after lining the channel and via openings with barrier material. First, a low temperature deposition of a seed layer is performed at below the 250° C. at which conductive material agglomeration occurs. Second, a higher temperature deposition of a seed layer is performed at above 250° C. Then, the conductive material is deposited to fill the channel and via openings.

Abstract: A method is provided for forming barrier layers in channel or via openings of semiconductors by using in-situ nitriding of barrier metals (Ta, Ti, or W) after they have been deposited in channel and via openings which will allow better control of the barrier metal/barrier material (Ta/TaN, Ti/TiN, or W/WN) composition, eliminate particle problems, and avoiding target poisoning.

Abstract: An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.

Abstract: A method is provided for forming tantalum/copper barrier/seed layers in semiconductor channels or vias by using a pulsed laser annealing step. The pulsed laser can be controlled to heat the copper seed material for such short periods of time that the copper seed material does not agglomerate but the temperature is high enough to form an intermixed layer with the tantalum.

Abstract: A semiconductor metalization barrier, and manufacturing method therefor, is provided which is a stack of a cobalt layer and cobalt tungsten layer deposited on a copper bonding pad.

Abstract: The present invention provides a method for forming barrier layers in a channel or via opening by using a plasma etching technique to etch back the barrier layer which reduces the electrical resistance of the barrier layer, maintains its barrier effectiveness and enhances the subsequent filling of the channel or via opening by conductive materials.

Abstract: Void free Cu or Cu alloy interconnects are formed by annealing at superatmospheric pressure after metallization. Embodiments include filling a damascene opening in a dielectric layer with Cu or a Cu alloy and heat treating in a chamber at a pressure of about 2 atmospheres to about 750 atmospheres.

Abstract: A method for implanting copper conductive layers in channel or via openings with alloying elements, such as magnesium, boron, tin, and zirconium. The implantation is performed after conductive layer chemical-mechanical-polishing (CMP) using a surface barrier layer as an implant barrier. With the surface barrier layer being removed by barrier layer CMP, this allows directed, heavy implantation of the conductive layer with the alloying elements.