Patents by Inventor Dirk Manger

Dirk Manger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7662721
    Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: February 16, 2010
    Assignee: Infineon Technologies AG
    Inventors: Dirk Manger, Hocine Boubekeur, Martin Verhoeven, Nicolas Nagel, Thomas Tatry, Dirk Caspary, Matthias Markert
  • Patent number: 7649779
    Abstract: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: January 19, 2010
    Assignees: Qimonda AG, Qimonda Flash GmbH
    Inventors: Eike Ruttkowski, Detlev Richter, Michael Specht, Joseph Willer, Dirk Manger, Kenny Oisin, Steffen Meyer, Klaus Knobloch, Holger Moeller, Doris Keitel Schulz, Jan Gutsche, Gert Koebernik, Christoph Friederich
  • Publication number: 20090321940
    Abstract: An integrated circuit is described including a first and a second plurality of conductor lines, each of the lines being separated from an adjacent line by a spacer dielectric and capped with a first and second dielectric cap material, respectively. A contact element is embedded in a covering dielectric layer with electrical contact to one of the first plurality of conductor lines in a contact portion, while being separated from a line adjacent to the contacted line only by the second cap material.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Gerhard Kunkel, Dirk Manger, Stephan Wege
  • Publication number: 20090309152
    Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 17, 2009
    Inventors: Roman Knoefler, Michael Specht, Franz Hofmann, Florian Beug, Dirk Manger, Stephan Riedel
  • Publication number: 20090239314
    Abstract: Methods of manufacturing a semiconductor device and an apparatus for the manufacturing of semiconductor devices are provided. An embodiment regards providing a process which changes the volume of at least one layer of a semiconductor substrate or of at least one layer deposited on the semiconductor substrate, and measuring a change in volume of such at least one layer using fluorescence. In another embodiment, a change in volume of such at least one layer is measured using reflection of electromagnetic waves.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Inventors: Martin Haberjahn, Sascha Dieter, Andrea Graf, Christoph Noelscher, Dirk Manger, Stephan Wege
  • Publication number: 20090075462
    Abstract: The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Inventors: Dirk Manger, Rolf Weis, Christoph Noelscher
  • Publication number: 20090033362
    Abstract: In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Inventors: Dirk Manger, Stephan Wege, Rolf Weis, Christoph Noelscher
  • Patent number: 7473952
    Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: January 6, 2009
    Assignee: Infineon Technologies AG
    Inventors: Dirk Manger, Stefan Slesazeck, Stefan Tegen, Klaus Muemmler, Alexander Sieck
  • Publication number: 20080285344
    Abstract: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Inventors: Eike Ruttkowski, Detlev Richter, Michael Specht, Joseph Willer, Dirk Manger, Kenny Oisin, Steffen Meyer, Klaus Knobloch, Holger Moeller, Doris Keitel Schulz, Jan Gutsche, Gert Koebernik, Christoph Friederich
  • Publication number: 20080237738
    Abstract: The present invention relates generally to integrated circuits, a cell, a cell arrangement, a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement and a memory module. In an embodiment of the invention, an integrated circuit having a cell is provided. The cell includes a first source/drain region, a second source/drain region, an active region between the first source/drain region and the second source/drain region, a gate insulating region disposed above the active region, a gate region disposed above the gate insulating region, and at least one metal structure below the first source/drain region or the second source/drain region.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 2, 2008
    Inventors: Christoph Andreas Kleint, Dirk Manger, Nicolas Nagel, Andreas Taeuber
  • Patent number: 7368752
    Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: May 6, 2008
    Assignee: Infineon Technologies AG
    Inventors: Richard J. Luyken, Franz Hofmann, Lothar Risch, Dirk Manger, Wolfgang Rösner, Till Schlösser, Michael Specht
  • Publication number: 20080054324
    Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at at least two opposite sides.
    Type: Application
    Filed: October 29, 2007
    Publication date: March 6, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Richard Luyken, Franz Hofmann, Lothar Risch, Dirk Manger, Wolfgang Rosner, Till Schloesser, Michael Specht
  • Patent number: 7339224
    Abstract: The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electrode, a dielectric layer (10) on the trench wall as capacitor dielectric and a metallic filler material (30?) provided in the trench (2) as second electrode. Above the conducting metallic filling material (30?) a dielectric filling material (35) is provided in the trench (2) with a cavity (40) provided for mechanical tensions. The invention further relates to a corresponding method of production.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: March 4, 2008
    Assignee: Infineon Technologies AG
    Inventor: Dirk Manger
  • Publication number: 20070269948
    Abstract: A two-bits-per-cell flash memory cell is based on a localized trapping storage mechanism. The memory cell may be programmed via a hot hole injection mechanism and erased via a Fowler-Nordheim electron tunneling mechanism. The memory cells are arranged according to a virtual-ground wiring scheme. Gate structures of the memory cells are arranged in columns, and the widths of the columns are essentially equal to the distance between the columns. Bit lines elongate in pairs between the columns of memory cells and connect corresponding impurity regions being associated to one of the columns of memory cells. Separation devices separating the bit lines of each pair of bit lines are formed symmetrically to the edges of the neighboring columns of memory cells. Program cross-talk issues, concerning memory cells sharing the same bit line, may be avoided while memory cell size remains essentially unaffected.
    Type: Application
    Filed: May 19, 2006
    Publication date: November 22, 2007
    Inventor: Dirk Manger
  • Publication number: 20070254442
    Abstract: A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 1, 2007
    Inventors: Dirk Manger, Jyoti Gupta, Christoph Ludwig, Hans Lindemann
  • Publication number: 20070243707
    Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
    Type: Application
    Filed: March 15, 2007
    Publication date: October 18, 2007
    Applicant: QIMONDA AG
    Inventors: Dirk Manger, Hocine Boubekeur, Martin Verhoeven, Nicolas Nagel, Thomas Tatry, Dirk Caspary, Matthias Markert, Lothar Bauch, Stefan Blawid, Manuela Gutsch, Ludovic Lattard, Martin Roessiger, Mirko Vogt
  • Publication number: 20070215986
    Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.
    Type: Application
    Filed: March 15, 2006
    Publication date: September 20, 2007
    Inventors: Dirk Manger, Hocine Boubekeur, Martin Verhoeven, Nicolas Nagel, Thomas Tatry, Dirk Caspary, Matthias Markert
  • Publication number: 20070114616
    Abstract: A field effect transistor, which is arranged in a semiconductor device, comprises a first and a second doped source/drain region, both regions being arranged within a semiconductor substrate on either side of a gate electrode, and a channel region formed within the substrate between both doped source/drain regions beneath said gate electrode. A gate oxide layer is formed upon the semiconductor substrate. The gate electrode contacts a surface of the gate oxide layer and further comprises at least a first and a second conductive layer, wherein the first and second conductive layers are made of materials having different work functions with respect to each other. The first conductive layer contacts the gate oxide layer within a first portion of the surface, and the second conductive layer contacts the gate oxide layer within a second portion of the surface. The first conductive layer is further conductively connected to the second conductive layer.
    Type: Application
    Filed: November 23, 2005
    Publication date: May 24, 2007
    Inventors: Dirk Manger, Till Schloesser
  • Publication number: 20070037345
    Abstract: A method of forming a memory cell array including a plurality of memory cells includes patterning isolation trenches on a semiconductor substrate and filling with an insulating material to define active area lines. In particular, the isolation trenches are patterned as straight lines, resulting in the active area lines being formed as straight lines. After forming word lines incorporating a plurality of gate electrodes, isolation grooves are formed by etching the semiconductor substrate material using the gate electrodes as an etching mask. The active area segments are isolated from each other by a self-aligned etching step. Thereafter, the transistors are completed by defining the first and second source/drain regions, and the remaining parts of the memory cells, in particular, the capacitor contacts, the bit lines and the storage capacitors are formed.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 15, 2007
    Inventor: Dirk Manger
  • Publication number: 20070034927
    Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a “buried” collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.
    Type: Application
    Filed: November 14, 2005
    Publication date: February 15, 2007
    Inventors: Harald Seidl, Dirk Manger, Matthias Goldbach, Albert Birner, Stefan Slesazeck