Patents by Inventor Dirk Robert Walter Leipold

Dirk Robert Walter Leipold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113240
    Abstract: A novel and useful mechanism of improving the controllability of the electrostatic potential profile and electric field between barrier/control gates separating quantum dots (QD) in a quantum dot array (QDA) and creating elongated double quantum dot array 2D structures each having capability for a continuous tunneling within the array structure. Plunger gates implemented as blind contacts improve electric field control between barrier gates in a quantum dot array. Blind contacts create a dedicated control potential under multiple blind contact electrodes placed on a metal layer of a standard FDSOI process. They function to control potential well depths independently for neighboring quantum dots. Two or more coupled quantum dots within one elongated active area enables interconnection of neighboring quantum dot chains using a conductive semiconductor well. The blind contacts enable the implementation of charge sensors, precise precharge transistors, and linear and 2D quantum dot array.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 4, 2024
    Inventors: Dirk Robert Walter Leipold, Elena Blokhina, Andrii Sokolov
  • Publication number: 20240047295
    Abstract: The present disclosure relates to a three-dimensional (3D) package that has a die-on-die configuration, and includes a first die and at least one second die deposed underneath the first die. The first die includes a back-end-of-line (BEOL) portion, a device region over the BEOL portion, a substrate over the device region, and a substrate tie structure that extends through the device region and at least extends into the substrate. The substrate and the substrate tie structure each has a high thermal conductivity higher than 50 W/mK. The at least one second die is configured to be coupled to the BEOL portion of the first die, such that heat generated by the second die can propagate through the BEOL portion and the substrate tie structure, and radiate out of the first substrate.
    Type: Application
    Filed: December 13, 2021
    Publication date: February 8, 2024
    Inventors: George Maxim, Julio C. Costa, Dirk Robert Walter Leipold, Baker Scott
  • Publication number: 20240039482
    Abstract: A broadband low noise amplifier (LNA) structure (10) includes a main LNA (12), an offset LNA (14), an input splitter (16), and an output combiner (18). The input splitter (16) is configured to split a radio frequency (RF) input signal into a first RF input signal and a second RF input signal with difference phases, which are fed to the main LNA (12) and the offset LNA (14), respectively. Based on the first RF input signal, the main LNA (12) is configured to provide a first RF output signal, and based on the second RF input signal, the offset LNA (14) is configured to provide a second RF output signal. The output combiner (18) is configured to realign the first RF output signal and the second RF output signal, and configured to combine the first and second RF output signals to provide a combined RF output signal.
    Type: Application
    Filed: December 20, 2021
    Publication date: February 1, 2024
    Inventors: Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 11864352
    Abstract: A novel and useful system wiring apparatus and related techniques that address the need to feed power and electronic signals to and from a sample board between the cold, low pressure region in a vacuum chamber and outside room temperature and atmospheric pressure. The wiring apparatus balances electrical resistance with the thermal conductivity of the power and signal conductors. Printed flexible cables are used having an annular sealing region which together with O-rings provide vacuum sealing while allowing electrical signals to pass between integrated circuit(s) inside the vacuum chamber and equipment outside the chamber. A thermal anchor is placed along the printed flexible cable to maintain a desired temperature along the cable. The printed flexible circuits are multilayer with two outer layers serving as an RF shield while two inner layers comprise the signal lines which typically require shielding, electrical isolation from each other and from external electromagnetic fields.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: January 2, 2024
    Assignee: EQUAL 1 LABORATORIES IRELAND LIMITED
    Inventors: Hans Haenlein, Dirk Robert Walter Leipold, Ali Esmailiyan
  • Publication number: 20230403784
    Abstract: A novel and useful system wiring apparatus and related techniques that address the need to feed power and electronic signals to and from a sample board between the cold, low pressure region in a vacuum chamber and outside room temperature and atmospheric pressure. The wiring apparatus balances electrical resistance with the thermal conductivity of the power and signal conductors. Printed flexible cables are used having an annular sealing region which together with O-rings provide vacuum sealing while allowing electrical signals to pass between integrated circuit(s) inside the vacuum chamber and equipment outside the chamber. A thermal anchor is placed along the printed flexible cable to maintain a desired temperature along the cable. The printed flexible circuits are multilayer with two outer layers serving as an RF shield while two inner layers comprise the signal lines which typically require shielding, electrical isolation from each other and from external electromagnetic fields.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Hans HAENLEIN, Dirk Robert Walter LEIPOLD, Ali ESMAILIYAN
  • Publication number: 20230403825
    Abstract: A novel and useful system wiring apparatus and related techniques that address the need to feed power and electronic signals to and from a sample board between the cold, low pressure region in a vacuum chamber and outside room temperature and atmospheric pressure. The wiring apparatus balances electrical resistance with the thermal conductivity of the power and signal conductors. Printed flexible cables are used having an annular sealing region which together with O-rings provide vacuum sealing while allowing electrical signals to pass between integrated circuit(s) inside the vacuum chamber and equipment outside the chamber. A thermal anchor is placed along the printed flexible cable to maintain a desired temperature along the cable. The printed flexible circuits are multilayer with two outer layers serving as an RF shield while two inner layers comprise the signal lines which typically require shielding, electrical isolation from each other and from external electromagnetic fields.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Hans HAENLEIN, Dirk Robert Walter LEIPOLD, Ali ESMAILIYAN
  • Publication number: 20230403803
    Abstract: A novel and useful system wiring apparatus and related techniques that address the need to feed power and electronic signals to and from a sample board between the cold, low pressure region in a vacuum chamber and outside room temperature and atmospheric pressure. The wiring apparatus balances electrical resistance with the thermal conductivity of the power and signal conductors. Printed flexible cables are used having an annular sealing region which together with O-rings provide vacuum sealing while allowing electrical signals to pass between integrated circuit(s) inside the vacuum chamber and equipment outside the chamber. A thermal anchor is placed along the printed flexible cable to maintain a desired temperature along the cable. The printed flexible circuits are multilayer with two outer layers serving as an RF shield while two inner layers comprise the signal lines which typically require shielding, electrical isolation from each other and from external electromagnetic fields.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Inventors: Hans HAENLEIN, Dirk Robert Walter LEIPOLD, Ali ESMAILIYAN
  • Publication number: 20230387042
    Abstract: The present disclosure describes a front-end module (FEM) and a process for making the same. In the disclosed FEM, a thinned flip-chip die, which includes a device region with a metal layer, resides over a module carrier. A mold compound resides over the module carrier, surrounds the thinned flip-chip die, and extends beyond a top surface of the thinned flip-chip die to define an opening over the top surface of the thinned flip-chip die and within the mold compound. A ferrimagnetic portion resides over the top surface of the thinned flip-chip die and within the opening, and a permanent magnetic portion resides over the ferrimagnetic portion and within the opening. Herein, the permanent magnetic portion, the ferrimagnetic portion, and the metal layer of the device region are vertically aligned, and form a circulator vertically stacked with the thinned flip-chip die.
    Type: Application
    Filed: December 13, 2021
    Publication date: November 30, 2023
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 11822163
    Abstract: A novel and useful quantum computing machine includes classic computing and quantum computing cores. A programmable pattern generator executes instructions that control the quantum core. A pulse generator generates the control signals input to the quantum core to perform quantum operations. A partial readout of the quantum state is re-injected into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the readout before being re-injected into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or retrieved from classic memory where sequences of commands are stored in memory. A cryostat unit functions to cool the quantum computing core to approximately 4 Kelvin.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 21, 2023
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11699978
    Abstract: Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: July 11, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold
  • Patent number: 11635642
    Abstract: A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core.
    Type: Grant
    Filed: December 18, 2021
    Date of Patent: April 25, 2023
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11611032
    Abstract: A novel and useful modified semiconductor fabrication technique for realizing reliable semiconductor quantum structures. Quantum structures require a minimization of the parasitic capacitance of the control gate and the quantum well. The modified semiconductor process eliminates the fabrication of the metal, contact, and optionally the raised diffusion layers from the quantum wells, thereby resulting in much lower well and gate capacitances and therefore larger Coulomb blockade voltages. This allows easier implementation of the electronic control circuits in that they can have larger intrinsic noise and relaxed analog resolution. Several processes are disclosed including implementations of semiconductor quantum structures with tunneling through an oxide layer as well as tunneling through a local well depleted region. These techniques can be used in both planar semiconductor processes and 3D, e.g., FinFET, semiconductor processes. A dedicated process masking step is used for realizing the raised diffusions.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: March 21, 2023
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11533046
    Abstract: A novel and useful system and method of generating quantum unitary noise using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. A detector circuit connected to the device outputs a digital stream corresponding to the probability of a particle of being detected. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: December 20, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: David J. Redmond, Dirk Robert Walter Leipold, Imran Bashir, Robert Bogdan Staszewski
  • Patent number: 11454834
    Abstract: Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 27, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11454833
    Abstract: Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 27, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11450760
    Abstract: Novel and useful quantum structures having a continuous fully depleted well with control gates that form two quantum dot on either side of the gate. Appropriate potentials are applied to the well and control gate to control quantum tunneling between quantum dots thereby enabling quantum operations to occur. Qubits are realized by modulating applied gate potential to control tunneling through a quantum transport path between two or more sections of the well. Complex structures with a higher number of quantum dots per continuous well and a larger number of wells can be fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. An injection device permits tunneling of a single quantum particle from a classic side to a quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: September 20, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11423322
    Abstract: A novel and useful fully integrated quantum computer containing both quantum core circuitry and associated classical electronic control circuits on the same monolithic die. The integrated quantum computer avoids ESD loading on the quantum structures and minimizes the need for long interconnects with resultant large parasitic inductances and capacitances. Such parasitics reduce the maximum operating frequency of the realized quantum core structures. A cryostat unit functions to provide several temperatures to the quantum computer including a temperature to cool the quantum core to approximately 4° K and the interface SoC to 77° K. Alternatively, the interface circuitry is also integrated with the main QPU on the same die. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations.
    Type: Grant
    Filed: January 5, 2020
    Date of Patent: August 23, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Patent number: 11366345
    Abstract: Novel and useful quantum structures that provide various control functions. Particles are brought into close proximity to interact with one another and exchange information. After entanglement, the particles are moved away from each other but they still carry the information contained initially. Measurement and detection are performed on the particles from the entangled ensemble to determine whether the particle is present or not in a given qdot. A quantum interaction gate is a circuit or structure operating on a relatively small number of qubits. Quantum interaction gates implement several quantum functions including a controlled NOT gate, quantum annealing gate, controlled SWAP gate, a controlled Pauli rotation gate, and ancillary gate. These quantum interaction gates can have numerous shapes including double V shape, H shape, X shape, L shape, I shape, etc.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 21, 2022
    Assignee: Equal1.Labs Inc.
    Inventors: Dirk Robert Walter Leipold, George Adrian Maxim, Michael Albert Asker
  • Publication number: 20220147824
    Abstract: A novel and useful system and method of accelerated learning in neural networks using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability. The quantum unitary noise is injected into one or more layers of an artificial neural network (ANN) to improve the learning and training process.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 12, 2022
    Inventors: David J. REDMOND, Dirk Robert Walter LEIPOLD, Imran BASHIR, Robert Bogdan STASZEWSKI
  • Publication number: 20220149823
    Abstract: A novel and useful system and method of generating quantum unitary noise using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. A detector circuit connected to the device outputs a digital stream corresponding to the probability of a particle of being detected. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 12, 2022
    Inventors: David J. REDMOND, Dirk Robert Walter LEIPOLD, Imran BASHIR, Robert Bogdan STASZEWSKI