Patents by Inventor Dirk Robert Walter Leipold

Dirk Robert Walter Leipold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10448516
    Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 15, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10447344
    Abstract: Improved Radio Frequency (RF) switches are provided herein. According to one aspect, an RF switch comprises one or more stages. In one embodiment, each stage comprises a signal input terminal, a signal output terminal, a control input terminal, and a switching device having a first terminal connected to the signal input terminal, a second terminal connected to the signal output terminal, and a third terminal for controlling the on/off state of the switching device. Each stage includes a first resistor connected in series between the control input terminal and the third terminal, a first bypass switch for electrically bypassing the first resistor, and a second resistor connected in series between the signal input terminal and the signal output terminal. The first resistors form a first bias network, the second resistors form a second bias network, and the switching devices are connected in series.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 15, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold, Eric K. Bolton, Daniel Charles Kerr, Hideya Oshima
  • Patent number: 10447222
    Abstract: Dynamic error vector magnitude (EVM) compensation is accomplished for radio frequency (RF) power amplifiers (PAs) which experience EVM distortion from thermal settling. Thermal settling causes gain changes in the PAs, and systems, apparatuses, and methods of the present disclosure compensate for known thermal transients of PAs.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 15, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, David Reed, Christopher T. Brown, Dirk Robert Walter Leipold, George Maxim
  • Publication number: 20190304977
    Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Julio C. Costa, Michael Carroll, Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 10431523
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10405433
    Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 3, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Publication number: 20190267956
    Abstract: A power amplifier apparatus supporting reverse intermodulation product (rIMD) cancellation is provided. The power amplifier apparatus includes an amplifier circuit configured to amplify and output a radio frequency (RF) signal for transmission via an antenna port. The antenna port may receive a reverse interference signal, which may interfere with the RF signal to create a rIMD(s) that can fall within an RF receive band(s). A reverse coupling circuit is provided in the power amplifier apparatus to generate an interference cancellation signal based on the reverse interference signal. The amplifier circuit is configured to amplify the interference cancellation signal and the RF signal to create an intermodulation product(s) to suppress the rIMD(s) to a determined threshold. By suppressing the rIMD(s) in the power amplifier apparatus, it is possible to support concurrent transmissions and receptions in a number of RF spectrums while in compliance with stringent regulatory spurious emissions (SEM) requirements.
    Type: Application
    Filed: June 26, 2018
    Publication date: August 29, 2019
    Inventors: Marcus Granger-Jones, Dirk Robert Walter Leipold, Nadim Khlat
  • Publication number: 20190260335
    Abstract: Radio frequency (RF) filters configured to filter undesired signal components (e.g., noise and harmonics) from RF signals are disclosed. In one embodiment, an RF filter includes a first inductor coil having a first winding and a second inductor coil having a second winding and a third winding. The second winding of the second inductor coil is configured to have a first mutual magnetic coupling with the first winding, while the third winding of the second inductor coil is configured to have a second mutual magnetic coupling with the first winding. The second winding is connected to the third winding such that the first mutual magnetic coupling and the second mutual magnetic coupling are in opposition. In this manner, the first inductor coil and the second inductor coil may be provided in a compact arrangement while providing weak mutual magnetic coupling between the first inductor coil and the second inductor coil.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventors: Dirk Robert Walter Leipold, George Maxim, Baker Scott, Danny W. Chang
  • Publication number: 20190260345
    Abstract: Embodiments of radio frequency (RF) filtering circuitry are disclosed. In one embodiment, the RF filtering circuitry includes a first port, a second port, a first RF filter path, and a second RF filter path. The first RF filter path is connected between the first port and the second port and includes at least a pair of weakly coupled resonators. The weakly coupled resonators are configured such that a first transfer response between the first port and the second port defines a first passband. The second RF filter path is coupled to the first RF filter path and is configured such that the first transfer response between the first port and the second port defines a stopband adjacent to the first passband without substantially increasing ripple variation of the first passband defined by the first transfer response.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 22, 2019
    Inventors: Dirk Robert Walter Leipold, George Maxim, Marcus Granger-Jones, Baker Scott
  • Patent number: 10381289
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 13, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10374788
    Abstract: Embodiments of the disclosure relate to a phase locked loop (PLL)-less millimeter wave (mmWave) power head. The mmWave power head receives a multiplexed signal including a pilot signal at a base frequency and a communication signal at the IF frequency. The mmWave power head separates the pilot signal from the communication signal and multiplies the pilot signal to generate a local oscillator (LO) clock signal(s) at a harmonic frequency(ies) relative to the base frequency of the pilot signal. A selected LO clock signal is provided to a mixer circuit(s) for up and down conversions between the IF frequency and the mmWave carrier frequency. By eliminating the PLL frequency synthesizer from the mmWave power head, it is possible to avoid spur and coupling issues associated with collocating the PLL frequency synthesizer with an antenna front end module (FEM), thus helping to improve reliability and performance of the mmWave power head.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: August 6, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 10361667
    Abstract: Embodiments of the disclosure relate to a low noise amplifier (LNA) circuit. The LNA circuit includes an LNA configured to amplify a radio frequency (RF) input signal to generate an RF output signal. The LNA may be inherently nonlinear and, as a result, can create a harmonic distortion(s), such as second harmonic distortion (HD2), and/or an intermodulation distortion(s), such as second order intermodulation distortion (IMD2), in the RF output signal. In exemplary aspects discussed herein, a distortion amplifier(s) is provided in the LNA circuit to generate a distortion signal(s) to suppress the harmonic distortion(s) and/or the intermodulation distortion(s) in the RF output signal.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: July 23, 2019
    Assignee: Qorvo US, Inc.
    Inventors: George Maxim, Marcus Granger-Jones, Toshiaki Moriuchi, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10349529
    Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: July 9, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10340202
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 2, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10333479
    Abstract: Power amplifier circuitry includes an amplifier stage, a non-linear compensation network, and non-linear compensation control circuitry. The amplifier stage includes an input and an output, and is configured to receive an input signal at the input and provide an amplified output signal at the output. The non-linear compensation network is coupled between the input and the output of the amplifier stage. The non-linear compensation control circuitry is coupled to the non-linear compensation network and one or more of the input and the output of the amplifier stage. The non-linear compensation control circuitry is configured to adjust a capacitance of the non-linear compensation network to cancel a parasitic capacitance associated with the amplifier stage and thus reduce AM-PM distortion.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 25, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold
  • Patent number: 10326490
    Abstract: A multi radio access technology (RAT) circuit is provided. The multi RAT power management circuit can concurrently support multiple different RATs using a single power management integrated circuit and a single power amplifier. The multi RAT power management circuit receives a first digital signal modulated based on a first RAT and a second digital signal modulated based on a second RAT. Control circuitry generates a composite output signal, which includes the first digital signal and the second digital signal and corresponds to a time-variant composite signal envelope derived from a respective peak envelope of the first and the second digital signals. The control circuitry generates a voltage control signal having a time-variant target voltage envelope tracking the time-variant composite signal envelope of the composite output signal. As such, the multi RAT power management circuit can concurrently support the multiple different RATs without increasing size, costs, complexity, and/or power consumption.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 18, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Marcus Granger-Jones, Dirk Robert Walter Leipold
  • Publication number: 20190181813
    Abstract: Embodiments of the disclosure relate to a low noise amplifier (LNA) circuit. The LNA circuit includes an LNA configured to amplify a radio frequency (RF) input signal to generate an RF output signal. The LNA may be inherently nonlinear and, as a result, can create a harmonic distortion(s), such as second harmonic distortion (HD2), and/or an intermodulation distortion(s), such as second order intermodulation distortion (IMD2), in the RF output signal. In exemplary aspects discussed herein, a distortion amplifier(s) is provided in the LNA circuit to generate a distortion signal(s) to suppress the harmonic distortion(s) and/or the intermodulation distortion(s) in the RF output signal.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 13, 2019
    Inventors: George Maxim, Marcus Granger-Jones, Toshiaki Moriuchi, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10320339
    Abstract: Radio frequency (RF) filters configured to filter undesired signal components (e.g., noise and harmonics) from RF signals are disclosed. In one embodiment, an RF filter includes a first inductor coil having a first winding and a second inductor coil having a second winding and a third winding. The second winding of the second inductor coil is configured to have a first mutual magnetic coupling with the first winding, while the third winding of the second inductor coil is configured to have a second mutual magnetic coupling with the first winding. The second winding is connected to the third winding such that the first mutual magnetic coupling and the second mutual magnetic coupling are in opposition. In this manner, the first inductor coil and the second inductor coil may be provided in a compact arrangement while providing weak mutual magnetic coupling between the first inductor coil and the second inductor coil.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: June 11, 2019
    Assignee: Qirvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Baker Scott, Danny W. Chang
  • Patent number: 10304753
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: May 28, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10298196
    Abstract: Embodiments of radio frequency (RF) filtering circuitry are disclosed. In one embodiment, the RF filtering circuitry includes a first port, a second port, a first RF filter path, and a second RF filter path. The first RF filter path is connected between the first port and the second port and includes at least a pair of weakly coupled resonators. The weakly coupled resonators are configured such that a first transfer response between the first port and the second port defines a first passband. The second RF filter path is coupled to the first RF filter path and is configured such that the first transfer response between the first port and the second port defines a stopband adjacent to the first passband without substantially increasing ripple variation of the first passband defined by the first transfer response.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Marcus Granger-Jones, Baker Scott