Abstract: One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC decoded at a bus width which is specified within particular constraints. One constraint is that the FEC decoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC decoder bus width. Another constraint may be that the FEC decoder bus width is an exact multiple of a number of serial lanes of the multi-lane interface. Other embodiments and features are also disclosed.

Abstract: One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry.

Abstract: A configurable interface includes a transmitter module and a receiver module, each configured to operate according to at least three different interface standards. The configurable interface further includes an interface module configured to determine a physical medium attachment (PMA) standard of a PMA coupled to the configurable interface and activate at least one component of the configurable interface based on the PMA standard. In an arrangement, the device interface supports a CAUI-4 standard.

Abstract: The present disclosure provides physical coding sublayer architectures that enable high-speed serial interfaces capable of operating at data rates ranging from 400 gigabits per second (Gbps) to 1 terabit per second (Tbps). A first embodiment relates to an architecture that provides an aggregated physical coding sublayer (PCS) that provides multiple virtual lanes. A second embodiment relates to an architecture that has a channel-based PCS and provides an aggregation layer above the PCS channels. A third embodiment relates to an architecture that, like the second embodiment, has a channel-based PCS and provides an aggregation layer above the PCS channels. However, each channel-based PCS in the third embodiment provides multiple virtual lanes. Other embodiments, aspects and features are also disclosed.

Abstract: A method and system for operating a communication circuit during periods of reduced energy consumption are disclosed. Data may be transmitted over a communication link from a first device to a second device in a low-power state. The data may be used by the second device to update coefficients and/or synchronize the receiver of the second device to a transmitter of the first device, thereby enabling a more efficient or rapid transition from the low-power state to an active state. A transmitter of the first device and a receiver of the second device may be activated before transmission of the data and deactivated after transmission of the data. In this manner, a receiver of the second device may be refreshed to enable a more efficient transition from the low-power state to an active state.

Abstract: A method and system for transitioning a communication circuit to a low-power state are disclosed. Where a first device and a second device communicate over a communication link, the first device may initiate a transition from an active state to a low-power state to conserve energy. A symbol may be encoded by the first device in data and transmitted to the second device. The first device may deactivate one or more components when entering the low-power state. Additionally, responsive to receiving and decoding the symbol, the second device may deactivate one or more components when entering the low-power state. In this manner, energy consumption of one or more components can be reduced and a low-power state may be entered to conserve energy.

Abstract: A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.

Abstract: A method and system for efficiently transitioning a communication circuit from a low-power state are disclosed. A first device and second device in a low-power state may be transitioned to an active state to enable the transmission of data over a communication link, where energy consumption of one or more components of the first and/or second devices may be reduced in the low-power state. The transition may be initiated by the first device responsive to a signal and/or an expiration of a timer. Responsive thereto, a scrambler of the first device may be temporarily bypassed to accelerate achieving block lock at the second device, thereby enabling the system to more quickly transition from the low-power state to the active state.

Abstract: A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.

Abstract: Structures and methods are disclosed relating to a multi-protocol transceiver including lane-based Physical Coding Sublayer (“PCS”) circuitry that is configurable to adapt to one of a plurality of communication protocols. Particular embodiments of the present invention include lane based configurable data paths through PCS transmit and receive circuitry.

Abstract: One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry.

Abstract: An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.

Abstract: On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.

Abstract: An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.

Abstract: Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.

Abstract: Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.

Abstract: Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.

Abstract: Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.

Abstract: A serial interface for a programmable logic device includes receiver and transmitter portions, and an automatic speed negotiation module to adjust the data rates of both portions. The speed adjustment may be accomplished by adjusting the widths of the data paths in both portions. The speed adjustment occurs on receipt of a control signal generated elsewhere on the programmable logic device, or generated by the module. One reason for generating the control signal is the detection of data errors in the received data, or the detection of a delimiter pattern in the received data signifying that a remote device is about to change its data rate. Similarly, before changing its data rate, the module may insert a delimiter in the data in the transmitter portion. After receipt or transmission of a delimiter pattern, the module may wait for a predetermined delay period to elapse before changing the data rate.

Abstract: A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).