Patents by Inventor Dmitri E. Nikonov

Dmitri E. Nikonov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312086
    Abstract: An apparatus is provided which comprises: a first magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; a second magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; and a first layer of spin orbit coupling material adjacent to the first magnetic junction and the second magnetic junction via their respective 4-state free magnetic layers. Described is an apparatus which comprises a 4-state free magnetic layer; a layer of SOC material adjacent to the 4-state free magnetic layer; a first interconnect coupled to the layer of SOC material.
    Type: Application
    Filed: December 5, 2016
    Publication date: October 10, 2019
    Applicant: Intel Corporaration
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10439599
    Abstract: Embodiments include circuits, apparatuses, and systems for non-boolean associative processors. In embodiments, an electronic associative processor circuit may include first and second ring oscillators, each having an odd number of inverters, an input terminal, and an output terminal. A first capacitor may have a first terminal coupled with the output terminal of the first ring oscillator and a second capacitor may have a first terminal coupled with the output terminal of the second ring oscillator. Second terminals of the first and second capacitors may be coupled at an oscillator stage output terminal. The inverters of the first and second ring oscillators may be implemented with metal oxide semiconductor transistors. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Ian A. Young
  • Publication number: 20190259935
    Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.
    Type: Application
    Filed: December 23, 2016
    Publication date: August 22, 2019
    Inventors: Jasmeet S. CHAWLA, Sasikanth MANIPATRUNI, Robert L. BRISTOL, Chia-Ching LIN, Dmitri E. NIKONOV, Ian A. YOUNG
  • Patent number: 10361292
    Abstract: Antiferromagnetic magneto-electric spin-orbit read (AFSOR) logic devices are presented. The devices include a voltage-controlled magnetoelectric (ME) layer that switches polarization in response to an electric field from the applied voltage and a narrow channel conductor of a spin-orbit coupling (SOC) material on the ME layer. One or more sources and one or more drains, each optionally formed of ferromagnetic material, are provided on the SOC material.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: July 23, 2019
    Assignees: INTEL CORPORATION, THE RESEARCH FOUNDATION FOR THE STATE UNIVERSITY OF NEW YORK, BOARD OF REGENTS OF THE UNIVERSITY OF NEBRASKA, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Dmitri E. Nikonov, Christian Binek, Xia Hong, Jonathan P. Bird, Kang L. Wang, Peter A. Dowben
  • Patent number: 10347830
    Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Elijah Ilya Karpov, Brian Doyle, Dmitri E. Nikonov, Ian Young
  • Publication number: 20190198754
    Abstract: An apparatus is provided which comprises: a ferromagnetic (FM) region with magnetostrictive (MS) property; a piezo-electric (PZe) region adjacent to the FM region; and a magnetoelectric region adjacent to the FM region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; and a magnetoelectric region, wherein the FM region is at least partially adjacent to the magnetoelectric region. An apparatus is provided which comprises: a FM region with MS property; a PZe region adjacent to the FM region; a magnetoelectric region being adjacent to the FM and PZe regions; a first electrode adjacent to the FM and PZe regions; a second electrode adjacent to the magnetoelectric region; a spin orbit coupling (SOC) region adjacent to the magnetoelectric region; and a third electrode adjacent to the SOC region.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Publication number: 20190181249
    Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
    Type: Application
    Filed: July 1, 2016
    Publication date: June 13, 2019
    Inventors: SASIKANTH MANIPATRUNI, ANURAG CHAUDHRY, DMITRI E. NIKONOV, JASMEET S. CHAWLA, CHRISTOPHER J. WIEGAND, KANWALJIT SINGH, UYGAR E. AVCI, IAN A. YOUNG
  • Patent number: 10320404
    Abstract: Described is an oscillating apparatus which comprises: an interconnect with spin-coupling material (e.g., Spin Hall Effect (SHE) material); and a magnetic stack having two magnetic layers such that one of the magnetic layers is coupled to the interconnect, wherein each of the two magnetic layers have respective magnetization directions to cause the magnetic stack to oscillate.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Sasi Manipatruni, George I. Bourianoff, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10263036
    Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Asif Khan, Raseong Kim, Tahir Ghani, Ian A. Young
  • Publication number: 20190087717
    Abstract: One embodiment provides a four stable state neuron. The four stable state neuron includes a plurality of input elements and a plurality of coupling channels. Each input element is coupled to a respective coupling channel and each input element is to scale a respective two-dimensional input signal by a weight. The four stable state neuron further includes a first output element coupled to the plurality of coupling channels. The first output element is to receive the plurality of weighted two-dimensional input signals and to generate a two-dimensional output signal based, at least in part, on a threshold value.
    Type: Application
    Filed: April 1, 2016
    Publication date: March 21, 2019
    Applicant: Intel Corporation
    Inventors: Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov
  • Publication number: 20190036018
    Abstract: Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.
    Type: Application
    Filed: March 29, 2016
    Publication date: January 31, 2019
    Inventors: Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov, Ravi Pillarisetty, Uygar E. Avci
  • Publication number: 20190013063
    Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.
    Type: Application
    Filed: March 23, 2016
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Huichu LIU, Sasikanth MANIPATRUNI, Daniel H. MORRIS, Kaushik VAIDYANATHAN, Niloy MUKHERJEE, Dmitri E. NIKONOV, Ian YOUNG, Tanay KARNIK
  • Publication number: 20180331281
    Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: Sasikanth Manipatruni, Elijah Ilya Karpov, Brian Doyle, Dmitri E. Nikonov, Ian Young
  • Patent number: 10090034
    Abstract: A magnetoelectric memory cell with domain-wall-mediated switching is implemented using a split gate architecture. The split gate architecture allows a domain wall to be trapped within a magnetoelectric antiferromagnetic (MEAF) active layer. An extension of this architecture applies to multiple-gate linear arrays that can offer advantages in memory density, programmability, and logic functionality. Applying a small anisotropic in-plane shear strain to the MEAF can block domain wall precession to improve reliability and speed of switching.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: October 2, 2018
    Assignees: BOARD OF REGENTS OF THE UNIVERSITY OF NEBRASKA, THE JOHN HOPKINS UNIVERSITY, INTEL CORPORATION
    Inventors: Kirill D. Belashchenko, Oleg Tchernyshyov, Alexey Kovalev, Dmitri E. Nikonov
  • Patent number: 10062731
    Abstract: An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Publication number: 20180240896
    Abstract: Antiferromagnetic magneto-electric spin-orbit read (AFSOR) logic devices are presented. The devices include a voltage-controlled magnetoelectric (ME) layer that switches polarization in response to an electric field from the applied voltage and a narrow channel conductor of a spin-orbit coupling (SOC) material on the ME layer. One or more sources and one or more drains, each optionally formed of ferromagnetic material, are provided on the SOC material.
    Type: Application
    Filed: February 17, 2018
    Publication date: August 23, 2018
    Applicants: Board of Regents of the University of Nebraska, Intel Corporation, The Research Foundation for the State University of New York STOR - University at Buffalo, The Regents of the University of California
    Inventors: Dmitri E. NIKONOV, Christian BINEK, XIA HONG, Jonathan P. BIRD, Kang L. WANG, Peter A. DOWBEN
  • Publication number: 20180240583
    Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).
    Type: Application
    Filed: September 9, 2015
    Publication date: August 23, 2018
    Applicant: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Anurag Chaudhry, Ian A. Young
  • Publication number: 20180240964
    Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.
    Type: Application
    Filed: September 10, 2015
    Publication date: August 23, 2018
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Sasikanth Manipatruni, Anurag Chaudhry, Ian A. Young
  • Patent number: 10043971
    Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Elijah Ilya Karpov, Brian Doyle, Dmitri E. Nikonov, Ian Young
  • Publication number: 20180158588
    Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.
    Type: Application
    Filed: June 24, 2015
    Publication date: June 7, 2018
    Inventors: Sasikanth MANIPATRUNI, Anurag CHAUDHRY, Dmitri E. NIKONOV, Ian A. YOUNG