Abstract: A memory device includes a stack of memory die packages. Each memory die package includes at least two memory dies. A switch is electrically coupled to at least one of the memory die packages. A bond wire electrically couples the switch to a substrate of the memory device. Each memory die is also electrically coupled to the switch. Based on a received control signal, the switch selects which memory die is electrically and/or communicatively coupled to the substrate using the electrical connections between the memory dies and the bond wire that electrically couples the switch to the substrate.

Abstract: Aspects of a storage device are provided that apply advanced thermal throttling with multi-tier extreme thermal throttling. Initially, a controller determines whether a first temperature measurement indicates that a temperature of the memory meets a first thermal threshold associated with a first-tier extreme thermal throttling or a second thermal threshold associated with a second-tier extreme thermal throttling. Subsequently, the controller enables the first-tier extreme thermal throttling when the temperature measurement indicates that the temperature of the memory meets the first thermal threshold, or the controller enables the second-tier extreme thermal throttling when the temperature measurement indicates that the temperature of the memory meets the second thermal threshold. The controller then determines whether a second temperature measurement indicates that the temperature of the memory has decreased to avoid thermal shutdown of the storage device.

Abstract: The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

Abstract: During operation of a data storage device, a controller of the data storage device may initiate read/write operations based on workloads provided by a host device. When initiating the read/write operations, power consumption and the data rate of the data storage device are generally high. Over time, the data rate corresponding to the workload decreases. Thus, the power consumption may be decreased to correspond with the decreased data rate. In order to maintain a high efficiency while decreasing an amount of power utilized, the controller may duty cycle the data storage device to operate between performance states to maintain a high data rate while decreasing power consumption.

Abstract: Methods and apparatus for precise power cycle management in data storage devices are provided. One such apparatus is a data storage device that includes a non-volatile memory (NVM) and a processor coupled to the NVM. In such case, the processor is configured to determine a first peak power for a first power phase, operate the DSD at a first DSD power consumption that is less than the first peak power for the first power phase, determine a second peak power for a second power phase based on a residual power equal to a difference between a preselected average power threshold and the first DSD power consumption, and operate the DSD at a second DSD power consumption that is less than the second peak power for the second power phase.

Abstract: The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

Abstract: Aspects of a storage device including a memory and a controller are provided, which allow for error detection or data integrity checking during data transfer of write operations and read operations. The controller may be configured to generate data integrity information based on at least one data byte to be written to the memory, and to transfer the at least one data byte contemporaneously with the data integrity information on separate data paths to the memory. The controller may be configured to select between transferring data bus inversion information or the data integrity information based on whether a data integrity protection mode is active between the memory and the controller. The memory may be configured to receive the at least one data byte and the data integrity information from the controller, and detect whether an error exists in the at least one data byte based on the data integrity information.

Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

Abstract: Aspects of a storage device are provided which apply advanced thermal throttling in response to temperature changes based on multiple thermal power states for different types of cells, such as SLCs and MLCs. Initially, a controller determines that a temperature of the memory meets a thermal throttling threshold of a plurality of thermal throttling thresholds. Subsequently, the controller transitions into a thermal power state of a plurality of thermal power states when the temperature meets the thermal throttling threshold. The controller applies a thermal mitigation configuration associated with the thermal power state. The controller then determines that the temperature of the memory has reached a thermal equilibrium in the thermal power state based on the thermal mitigation configuration. Storage device performance is thus improved through advanced thermal throttling without compromising data integrity.

Abstract: Aspects of a storage device are provided that apply history-based prediction modeling in advanced thermal throttling. Initially, a controller determines a temperature prediction based one or more thermal mitigation parameters using a history-based prediction model. Subsequently, the controller determines whether the temperature prediction indicates that an actual temperature of the memory is expected to meet a thermal throttling threshold of a plurality of thermal throttling thresholds. The controller then transitions into a thermal power state of a plurality of thermal power states when the temperature prediction indicates that the actual temperature of the memory is expected to meet the thermal throttling threshold. The controller applies a thermal mitigation configuration associated with the thermal power state and determines that the temperature of the memory has reached a thermal equilibrium based on the thermal mitigation configuration.

Abstract: Aspects of a storage device are provided which apply advanced thermal throttling in response to temperature changes based on multiple thermal power states for different types of cells, such as SLCs and MLCs. Initially, a controller determines that a temperature of the memory meets a thermal throttling threshold of a plurality of thermal throttling thresholds. Subsequently, the controller transitions into a thermal power state of a plurality of thermal power states when the temperature meets the thermal throttling threshold. The controller applies a thermal mitigation configuration associated with the thermal power state. The controller then determines that the temperature of the memory has reached a thermal equilibrium in the thermal power state based on the thermal mitigation configuration. Storage device performance is thus improved through advanced thermal throttling without compromising data integrity.

Abstract: Aspects of a storage device are provided that apply history-based prediction modeling in advanced thermal throttling. Initially, a controller determines a temperature prediction based one or more thermal mitigation parameters using a history-based prediction model. Subsequently, the controller determines whether the temperature prediction indicates that an actual temperature of the memory is expected to meet a thermal throttling threshold of a plurality of thermal throttling thresholds. The controller then transitions into a thermal power state of a plurality of thermal power states when the temperature prediction indicates that the actual temperature of the memory is expected to meet the thermal throttling threshold. The controller applies a thermal mitigation configuration associated with the thermal power state and determines that the temperature of the memory has reached a thermal equilibrium based on the thermal mitigation configuration.

Abstract: Aspects of a storage device are provided that apply advanced thermal throttling with multi-tier extreme thermal throttling. Initially, a controller determines whether a first temperature measurement indicates that a temperature of the memory meets a first thermal threshold associated with a first-tier extreme thermal throttling or a second thermal threshold associated with a second-tier extreme thermal throttling. Subsequently, the controller enables the first-tier extreme thermal throttling when the temperature measurement indicates that the temperature of the memory meets the first thermal threshold, or the controller enables the second-tier extreme thermal throttling when the temperature measurement indicates that the temperature of the memory meets the second thermal threshold. The controller then determines whether a second temperature measurement indicates that the temperature of the memory has decreased to avoid thermal shutdown of the storage device.

Abstract: The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

Abstract: The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

Abstract: Methods and apparatus for precise power cycle management in data storage devices are provided. One such apparatus is a data storage device that includes a non-volatile memory (NVM) and a processor coupled to the NVM. In such case, the processor is configured to determine a first peak power for a first power phase, operate the DSD at a first DSD power consumption that is less than the first peak power for the first power phase, determine a second peak power for a second power phase based on a residual power equal to a difference between a preselected average power threshold and the first DSD power consumption, and operate the DSD at a second DSD power consumption that is less than the second peak power for the second power phase.

Abstract: The present disclosure generally relates to a method and device for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected in series or in parallel to the FIM. The individual bus multiplexers can be addressed by a chip enable (CE) command that identifies the specific bus multiplexer as well as the specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without creating signal interference (SI) or limiting transmission performance.

Abstract: For solid state drive (SSD) or other memory system formed of multiple memory dies, techniques are presented for operation in a standby mode with increased power savings. The memory dies are operable in a regular standby mode and in a low power standby mode. Based upon the amount of current each of the memory dies in the regular standby mode, when the device goes into standby the memory dies that draw higher amounts of current when in the regular standby mode are instead placed into the low power standby mode. The amount of current drawn by each of the memory die in the regular standby mode can be determined for each of the memory dies at die sort or as part of the memory test process, or can be determine by an assembled SSD itself.

Abstract: The present disclosure generally relates to thermal throttling a nonvolatile memory device in a data storage device. Nonvolatile memory devices can sustain higher temperatures for a limited duration of time as part of the lifecycle/operation of the device. By allowing for a small margin of time at a higher temperature of operation, the maximum capability of the data storage device is increased. In so doing, the data storage device reliability can be maintained while increasing the device performance.