Abstract: Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.

Abstract: A method of performing data transactions in a high performance persistent memory comprising, with a processor, updating data by writing new data to non-volatile memory (NVM) and receiving a done signal from a transaction accelerator communicatively coupled to the NVM. An apparatus for high performance persistent memory, comprising a processor, a memory controller communicatively coupled to the processor, and non-volatile memory communicatively coupled to the memory controller and processor, the non-volatile memory comprising an ACID transaction accelerator, in which the processor updates data on the non-volatile memory (NVM) by writing new data to the NVM, and receives a done signal from the an ACID transaction accelerator when the data has been updated.

Abstract: An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

Abstract: A method for context-modeling coding information of a video signal for compressing or decompressing the coding information is provided. An initial value of a function for probability coding of coding information of a video signal of an enhanced layer is determined based on coding information of a video signal of a base layer.

Abstract: Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.

Abstract: A method for context-modeling coding information of a video signal for compressing or decompressing the coding information is provided. An initial value of a function for probability coding of coding information of a video signal of an enhanced layer is determined based on coding information of a video signal of a base layer.

Abstract: Versioned memories using a multi-level cell (MLC) are disclosed. An example method includes comparing a global memory version to a block memory version, the global memory version corresponding to a plurality of memory blocks, the block memory version corresponding to one of the plurality of memory blocks. The example method includes determining, based on the comparison, which level in a multi-level cell of the one of the plurality of memory blocks stores checkpoint data.

Abstract: A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern.

Abstract: A method for context-modeling coding information of a video signal for compressing or decompressing the coding information is provided. An initial value of a function for probability coding of coding information of a video signal of an enhanced layer is determined based on coding information of a video signal of a base layer.

Abstract: Disclosed herein are a computing system, integrated circuit, and method to enhance retrieval of cached data. A tracking table is used to initiate a search for data from a location specified in the table, if the data is not in a first level of a multi-level cache hierarchy.

Abstract: Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint.

Abstract: A method and an apparatus of decoding a video signal are provided. The present invention includes the steps of parsing first coding information indicating whether a residual data of an image block in the enhanced layer is predicted from a corresponding block in the base layer, from the bitstream of the enhanced layer, and decoding the video signal based on the first coding information. And, the step of parsing includes the step of performing modeling of the first coding information based on second coding information indicating whether prediction information of the corresponding block in the base layer is used to decode the image block in the enhanced layer. Accordingly, the present invention raises efficiency of video signal processing by enabling a decoder to derive information on a prediction mode of a current block in a decoder instead of transferring the information to the decoder.

Abstract: A power management module can select one of a plurality of different operational modes for a hardware component in a computer system based on application performance and total computer system power consumption determined for each of the operational modes.

Abstract: A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern.

Abstract: Memory address translations are disclosed. An example memory controller includes an address translator to translate an intermediate memory address into a hardware memory address based on a function, the address translator to select the function based on at least a portion of the intermediate memory address, the intermediate memory address being identified by a processor. The example memory controller includes a cache to store the function in association with an address range of the intermediate memory sector, the intermediate memory address being within the intermediate memory sector. Further, the example memory controller includes a memory accesser to access a memory module at the hardware memory address.

Abstract: Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices.

Abstract: A hybrid. memory module. The module includes at least two heterogeneous memory devices and a memory buffer in communication with the memory devices to read data from any one of the memory devices and write the data to any other of the memory devices.

Abstract: In one embodiment, decoding of a video signal includes predicting at least a portion of a current image in a current layer based on at least a residual coded portion of a base image in a base layer and shift information for samples in the predicted current image.

Abstract: In one embodiment, decoding of a video signal includes predicting at least a portion of a current image in a current layer based on at least a portion of a base image in a base layer and shift information for samples in the predicted current image.

Abstract: A method and an apparatus of decoding a video signal are provided. The present invention includes the steps of parsing first coding information indicating whether a residual data of an image block in the enhanced layer is predicted from a corresponding block in the base layer, from the bitstream of the enhanced layer, and decoding the video signal based on the first coding information. And, the step of parsing includes the step of performing modeling the first coding information based on second coding information indicating whether prediction information of the corresponding block in the base layer is used to decode the image block in the enhanced layer. Accordingly, the present invention raises efficiency of video signal processing by enabling a decoder to derive information on a prediction mode of a current block in a decoder instead of transferring the information to the decoder.