Abstract: A battery case for a pouch-type secondary battery accommodates an electrode assembly therein, and includes a first case, a second case configured to cover the first case, a cup portion provided in at least one of the first case or the second case and has a space formed to accommodate the electrode assembly, and a side portion formed along an outer circumference of each of the first case and the second case. The side portion includes a sealing portion sealed by bringing the first case and the second case into contact with each other. The side portion also includes an insulation failure-preventing portion formed between the sealing portion and the cup portion and configured to accommodates a sealing material melted in the sealing portion. A battery case shaping apparatus and a secondary battery manufacturing method are also provided.

Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The electronic device comprises a receiving unit for receiving a command from an external source, a first buffer for storing a first data value, and an operation engine for loading the first data value from the first buffer in response to the command and performing an operation based on a predetermined calculation formula on the loaded first data value, wherein the first data value is at least one of a result data value obtained by the operation engine previously performing an operation based on the predetermined calculation formula or a query data value to be used for an operation based on the predetermined calculation formula.

Abstract: As one aspect of the present disclosure, a byte-addressable device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor, the volatile memory device, and a non-volatile storage device, wherein the controller may be further configured to communicate with the volatile memory device and the non-volatile storage device based on address information included in a request received from the host processor.

Abstract: Disclosed is a multi-constraint qubit allocation method and a quantum apparatus using the same. The method comprises generating an interaction graph representing a quantum circuit on the basis of the number of two-qubit gates, determining edge weights between connected nodes in the interaction graph by introducing a fitting coefficient for a decay effect, searching for an isomorphic part, layout graph, between target hardware and the interaction graph by graph matching, and performing frequency matching for a layout graph by searching for frequency allocated to each location of qubits by limiting unidirectional movement on each of an x-axis and a y-axis of a hardware plane of the target hardware to a range from ?1 to +1.

Abstract: An operation method includes buffering data chunks to be programmed in the multi-level cells in a write buffer; backing up at least one backup data chunk of the data chunks to a backup memory; determining a program sequence of the data chunks, the program sequence for programming a non-backup data chunk among the data chunks to the multi-level cells through a second step program operation of the multi-step program operation; and controlling the memory device to program the data chunks in the multi-level cells, based on the program sequence, by performing first and second step program operations of the multi-step program operation in a first page of the multi-level cells, the second step program operation performed in the first page later than another first step program operation performed in a second page subsequent to the first page.

Abstract: An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.

Abstract: As one aspect of the present disclosure, a memory access device is disclosed. The device comprises: a command manager configured to receive and manage one or more commands from a plurality of cores; a programming engine unit comprising one or more programming engines configured to perform calculations in response to the one or more commands; and a direct memory access (DMA) controller configured to perform at least one of read access and write access to a memory external to the memory access device in response to the one or more commands, wherein the command manager comprises a command memory configured to store the one or more commands, and a slot management unit configured to allocate one or more cores that correspond to the one or more commands, respectively, to the one or more programming engines in sequence.

Abstract: A lower sheet disposed below a display panel includes a heat radiation layer having a first side and a second side facing the first side. A first film layer is disposed on the first side of the heat radiation layer. A second film layer is disposed on the second side of the heat radiation layer. A first resin layer is disposed between the heat radiation layer and the first film layer. A second resin layer is disposed between the heat radiation layer and the second film layer. A sealing layer is disposed on lateral sides of the heat radiation layer. The sealing layer directly contacts an entirety of the lateral sides of the heat radiation layer, and directly contacts at least a portion of lateral sides of the first resin layer and the second resin layer.

Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The device includes: a plurality of clusters, wherein each of the plurality of clusters comprises a plurality of cores; mailboxes uniquely corresponding to each of the plurality of clusters; and a system bus, wherein the inter-process communication may be performed between a sending core and a receiving core of the plurality of cores, and if the sending core and the receiving core are included in the same cluster, a mailbox corresponding to the same cluster may be configured to perform the inter-process communication without going through the system bus, and if the sending core and the receiving core are included in different clusters, mailboxes corresponding to each of the different clusters may be configured to perform the inter-process communication via the system bus.

Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The device includes: a plurality of clusters, wherein each of the plurality of clusters comprises a plurality of cores; mailboxes uniquely corresponding to each of the plurality of clusters; and a system bus, wherein the inter-process communication may be performed between a sending core and a receiving core of the plurality of cores, and if the sending core and the receiving core are included in the same cluster, a mailbox corresponding to the same cluster may be configured to perform the inter-process communication without going through the system bus, and if the sending core and the receiving core are included in different clusters, mailboxes corresponding to each of the different clusters may be configured to perform the inter-process communication via the system bus.

Abstract: A method for processing multiple transactions converted from a single transaction is provided, which is performed by a processor including at least one core and includes converting a first transaction conforming to an instruction according to an instruction set architecture (ISA) into a plurality of second transactions conforming to the register size of the core, and transferring, by the load-store unit (LSU) of the core, the plurality of second transactions to the cache, in which the LSU may be configured to further transfer, to the cache, conversion information indicating whether the plurality of second transactions are converted from the first transaction.

Abstract: A memory controller includes a cache memory, a host control circuit, and a flash translation layer. The host control circuit receives a read command and a logical address from a host, reads out mapping information corresponding to the logical address from a buffer memory device, and caches the mapping information in the cache memory. The flash translation layer reads a physical address corresponding to the logical address from the mapping information cached in the cache memory.

Abstract: A multiprocessor system may include a plurality of processors including a first processor and a second processor; a first cache memory corresponding to the first processor; a second cache memory corresponding to the first processor and the second processor and storing a plurality of cache lines; and a controller manages data stored in the second cache memory. The second cache memory includes at least one first cache line in which data is written by the first processor and at least one second cache line in which data is written by the second processor. The controller: receives a command associated with a data update from the first processor, and in response to the command, sets the first cache line as a clean cache line or an invalidated cache line while not setting the second cache line as a clean cache line or an invalidated cache line.

Abstract: The present disclosure relates to a manycore system which includes a device memory configured to store data associated with a job requested to be offloaded from a host device, and a plurality of clusters. Each of the plurality of clusters includes a program memory configured to store a program associated with the job requested to be offloaded, a plurality of cores configured to execute one or more threads associated with the job, and a management module configured to allocate one or more tasks associated with the job to the plurality of cores based on job loads of the plurality of cores, and control thread execution corresponding to the one or more allocated tasks. Each core includes thread areas configured to independently store and track an execution state of each thread executed on the core, and each thread executed on the core is independently executed using a separate thread area.

Abstract: The present disclosure relates to a manycore system capable of asynchronous execution of a plurality of threads. The manycore system includes a device memory configured to store data associated with a job requested to be offloaded from a host device, and a plurality of clusters. Each cluster includes a plurality of cores configured to execute a plurality of threads associated with a plurality of tasks included in the job and a management module configured to control asynchronous execution of the plurality of threads by the plurality of cores. Each core includes a plurality of fetch units configured to fetch, from the program memory, instructions associated with threads executed on the cores, one or more execution units configured to execute operations associated with the threads executed on the cores, and a plurality of load and store units configured to load and store data associated with the threads executed on the cores.

Abstract: A multiprocessor system may include a plurality of processors including a first processor and a second processor; a first cache memory corresponding to the first processor; a second cache memory corresponding to the first processor and the second processor and storing a plurality of cache lines; and a controller manages data stored in the second cache memory. The second cache memory includes at least one first cache line in which data is written by the first processor and at least one second cache line in which data is written by the second processor. The controller: receives a command associated with a data update from the first processor, and in response to the command, sets the first cache line as a clean cache line or an invalidated cache line while not setting the second cache line as a clean cache line or an invalidated cache line.

Abstract: It is one object of the present disclosure to provide measures for securing scalability of the queue depth of cache schedulers by utilizing a plurality of cache schedulers. To this end, a cache memory device in accordance with one embodiment of the present disclosure comprises: a request reception unit configured to receive input transactions; a traffic monitoring module configured to monitor traffic of the input transactions; N cache schedulers, wherein N is an integer greater than or equal to 2; a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers.

Abstract: A multi-threading processor is provided, which includes a cache including a memory and a controller, and a core electrically connected to the cache and configured to simultaneously execute and manage a plurality of threads, in which the core is configured to determine an occurrence of a data hazard for the plurality of threads and stall operations of the plurality of threads, receive, from the cache, hint information instructing a first thread of the plurality of threads to operate, and initiate an operation of the first thread based on the hint information while the data hazard for the plurality of threads is maintained.

Abstract: A memory controller includes a cache memory, a host control circuit, and a flash translation layer. The host control circuit receives a read command and a logical address from a host, reads out mapping information corresponding to the logical address from a buffer memory device, and caches the mapping information in the cache memory. The flash translation layer reads a physical address corresponding to the logical address from the mapping information cached in the cache memory.

Abstract: The present disclosure relates to a manycore system capable of asynchronous execution of a plurality of threads. The manycore system includes a device memory configured to store data associated with a job requested to be offloaded from a host device, and a plurality of clusters. Each cluster includes a plurality of cores configured to execute a plurality of threads associated with a plurality of tasks included in the job and a management module configured to control asynchronous execution of the plurality of threads by the plurality of cores. Each core includes a plurality of fetch units configured to fetch, from the program memory, instructions associated with threads executed on the cores, one or more execution units configured to execute operations associated with the threads executed on the cores, and a plurality of load and store units configured to load and store data associated with the threads executed on the cores.