Abstract: A method for inputting and/or outputting signals having a selectable sample rate in a time-synchronized manner on a group of input and/or output channels of an electronic circuit includes: configuring each channel of the group at a standard sample period; synchronously initiating all the channels of the group at the standard sample period; detecting an entry for a modified sample period TPeriod of a first channel of the group; detecting a current counter value TCounter; configuring the first channel at the modified sample period; establishing a waiting time of TWaiting clocks in accordance with TWaiting=TPeriod?mod(TCounter, TPeriod), where mod (TCounter, TPeriod) denotes the division remainder from the current counter value TCounter and the modified sample period TPeriod; and initiating the first channel after the waiting time TWaiting.

Abstract: A computer-implemented method for creating a hierarchical block diagram in a graphical development environment includes: automatically creating a hierarchical black box for a respective further subsystem block. The hierarchical black box is configured to resolve a corresponding hierarchical level when selected by a user. The automatic creation is carried out via a callback function. The hierarchical black box has the following features: at least one interface description and/or graphical representation of the inputs/outputs of the respective further subsystem block in its hierarchical level, which the respective further subsystem block previously also occupied; at least one reference to model content for the respective further subsystem block, comprising further black boxes for the further subsystem blocks in the subordinate hierarchical levels; parameters that the respective further subsystem block previously also had; and generated source code of the respective further subsystem block.

Abstract: A method for preparing an FPGA build result of an FPGA model is provided. The method includes designating an FPGA subsystem to configure a set of FPGA functions of the FPGA model. A pre-scaling subsystem and a post-scaling subsystem of the FPGA model are designated for execution on a processor. Internal and external interfaces are designated in the pre-scaling subsystem and post-scaling subsystem, where the internal interfaces ensure a data flow within the FPGA model, and the external interfaces ensure a data flow away from the FPGA model. Overall FPGA functionality is generated and the FPGA build result is generated on the basis of the generated overall FPGA functionality, where the FPGA build result includes a single master container file. The FPGA build result is provided to a further application for determining a set of functions of an entire model that includes the FPGA model and a processor model.

Abstract: In an FPGA, errors within an FPGA are detected by: providing at least one computation operation in the configurable logic block, a parity-invariant additional result being added, the parity-invariant additional result being provided by picking off an XOR bit of an XOR operation of the full adder, the XOR operation comprising at least two input signals; forming the parity of the XOR operation of the input signals with the aid of the following formula, and providing a parity signal: Parity(XOR(x1,x2)); calculating the XOR operation of the carried parities (Parity(x1), Parity(x2)) of the input signals with the aid of the device for checking the parity, using the following formula: XOR(Parity(x1), Parity(x2)); checking the parity, using a check of the truth of the following formula: XOR(Parity(x1), Parity(x2))==Parity(XOR(x1,x2); detecting an error in routes/calculations within the FPGA in the presence of an untrue statement of the formula of the preceding step.

Abstract: In an FPGA, a memory of the FPGA is to be effectively increased. This is achieved by a computer-implemented method for implementing a model-adaptive cache memory having a model state-dependent memory look-ahead on the FPGA.

Abstract: A method for programming an FPGA, wherein a library with elementary operations and a respective latency table for each of the elementary operations of the library are provided. a data path is defined. The latencies are recorded for a multiplicity of clock rates that are different from one another and these latencies are added for every clock rate so that a total latency for the data path results for this multiplicity of different clock rates. The ratio between the lowest total latency and the total latency at a respective clock rate is determined. A utilization of the FPGA for each clock rate is identified. The ratio between the lowest utilization of the FPGA and the utilization of the FPGA at a respective clock rate is determined. A quality factor for each clock rate while taking into account the total latency and the utilization of the FPGA is determined.

Abstract: A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.

Abstract: A method for documenting computing steps of a real time system executed on a computer core of a processor, wherein tasks are executed on the computer core, which include one or more subtasks, and wherein during a computing step in each case a subtask of a task is executed. A first processor time is recorded at the beginning and a second processor time is recorded at the end of a computing step and time information dependent on the first and second processor times is stored in memory. The time information is stored in memory in such a way that it can be assigned to the subtask and the task that was executed during the computing step.

Abstract: A computer-implemented method for creating a hierarchical block diagram in a graphical development environment includes: automatically creating a hierarchical black box for a respective further subsystem block. The hierarchical black box is configured to resolve a corresponding hierarchical level when selected by a user. The automatic creation is carried out via a callback function. The hierarchical black box has the following features: at least one interface description and/or graphical representation of the inputs/outputs of the respective further subsystem block in its hierarchical level, which the respective further subsystem block previously also occupied; at least one reference to model content for the respective further subsystem block, comprising further black boxes for the further subsystem blocks in the subordinate hierarchical levels; parameters that the respective further subsystem block previously also had; and generated source code of the respective further subsystem block.

Abstract: A method for changing a bitwidth of an FPGA configuration for an FPGA, the FPGA configuration having a plurality of at least 2n bit-containing data signals with n? and ?3, and the method having the step: when a threshold of a current consumption and/or a temperature of the FPGA is exceeded and/or a replacement signal is present, replacing k least significant bits of the data signals in each case with a zero with k? and ?2 during an execution of the FPGA configuration on the FPGA.

Abstract: A method is provided for data communication between at least one subregion of an FPGA and another region, in which the data communication is resource efficient. This is achieved by the fact that the data communication, i.e., the reading and writing of a Block RAM from a location to any Block RAM or from any Block RAM to any Block RAM of the FPGA takes place via command sequences of an internal configuration interface of the FPGA.

Abstract: A method for inputting and/or outputting signals having a selectable sample rate in a time-synchronized manner on a group of input and/or output channels of an electronic circuit includes: configuring each channel of the group at a standard sample period; synchronously initiating all the channels of the group at the standard sample period; detecting an entry for a modified sample period TPeriod of a first channel of the group; detecting a current counter value TCounter; configuring the first channel at the modified sample period; establishing a waiting time of TWaiting clocks in accordance with TWaiting=TPeriod?mod(TCounter, TPeriod), where mod(TCounter, TPeriod) denotes the division remainder from the current counter value TCounter and the modified sample period TPeriod; and initiating the first channel after the waiting time TWaiting.

Abstract: The object of the invention is a method of adding another circuit component (1) with operations executable on an FPGA to an FPGA configuration (3), wherein the FPGA configuration (3) already has at least one existing circuit component (2) with operations executable on the FPGA, which is locally distributed in the FPGA configuration (3), with the steps of: Synthesizing the further circuit component (1) to obtain a further netlist, and distributed arranging of the further netlist taking into account the at least one existing circuit component (2) in the FPGA configuration (3).

Abstract: A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

Abstract: A method for programming an FPGA, wherein a library, which includes elementary operations and a particular latency table for each of the elementary operations of the library is provided. Each latency table indicates the latency of the particular operation for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the particular operation during the execution on the FPGA, depending on the input bit width of the particular operation and the clock rate of the FPGA. A data path indicating a consecutive execution of at least two elementary operations of the library on the FPGA is defined. The latencies given for the particular input bit width of the particular elementary operations of the data path for a plurality of different clock rates in the latency tables are detected and added, then one of the clock rates is selected.

Abstract: A method for dividing a graphical simulation model up into a first sub-model and a second sub-model includes: identifying at least one first block as belonging to the first sub-model and identifying at least one second block as belonging to the second sub-model based on a sampling time and/or a resource allocation; searching for cyclic groups of blocks, wherein a cyclic group whose blocks all have the same sampling time is deemed to be atomic; identifying non-cyclic groups of blocks; allocating individual blocks from the cyclic groups of blocks and the non-cyclic group of blocks to either the first sub-model or the second sub-model, wherein all blocks of an atomic cyclic group are allocated to the same sub-model; generating program code for the processor from the first sub-model; and generating a configuration bitstream for the programmable logic module from the second sub-model.

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.