Abstract: A method for dividing a graphical simulation model up into a first sub-model and a second sub-model includes: identifying at least one first block as belonging to the first sub-model and identifying at least one second block as belonging to the second sub-model based on a sampling time and/or a resource allocation; searching for cyclic groups of blocks, wherein a cyclic group whose blocks all have the same sampling time is deemed to be atomic; identifying non-cyclic groups of blocks; allocating individual blocks from the cyclic groups of blocks and the non-cyclic group of blocks to either the first sub-model or the second sub-model, wherein all blocks of an atomic cyclic group are allocated to the same sub-model; generating program code for the processor from the first sub-model; and generating a configuration bitstream for the programmable logic module from the second sub-model.

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

Abstract: A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.

Abstract: A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

Abstract: Computer network having a plurality of clocks that are synchronized with one another, that are distributed among multiple participants in the computer network, and from which a global system time of the computer network can be read out. The computer network includes a first synchronizing signal transmitter for a first synchronizing signal and a second synchronizing signal transmitter for a second synchronizing signal, and every participant can be equipped to synchronize the value of a locally stored variable quantity with a global value on the basis of the first synchronizing signal or the second synchronizing signal, and in doing so to take into account a time lag of the synchronizing signal.

Abstract: A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

Abstract: A method for creating an FPGA netlist generated from an FPGA source code and at least one shadow register. The FPGA source code defines at least one function and at least one signal. The shadow register is assigned to the at least one signal, and is arranged and provided to store the value of the assigned signal at runtime. An option for reading out the stored signal value at runtime is provided. The function defined in the FPGA source code is not changed by the shadow register. The function described by the FPGA source code is executed by the FPGA, and a functional decoupling of the shadow register from the function described in the FPGA source code is provided. Via the decoupling, the shadow register maintains the signal value stored at the time of the decoupling while the function described in the FPGA source code is being executed.

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

Abstract: A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

Abstract: A method for reading variables from a Field Programmable Gate Array (FPGA) at runtime includes: calculating, in the FPGA, a first variable, wherein the first variable is associated with a first shadow register and a second shadow register, and wherein the first variable is associated with a first measurement grid and with a second measurement grid; synchronously storing, at a first point in time, all variables associated with the first measurement grid in shadow registers associated with the respective variables; synchronously storing, at a second point in time, all variables associated with the second measurement grid in shadow registers associated with the respective variables; and reading out the shadow registers independently of one another.

Abstract: A method for detecting the topology of electrical wiring between at least two field-programmable gate arrays (FPGAs) includes implementing a first receive register on a second interface pin; implementing a first send register on a first driver; activating the first driver via a first activation signal; emitting, by the first driver, a first signal, wherein the first signal is defined by the first send register; reading out, by a first receive register, whether the first signal is received at the second interface pin; and allocating the second interface pin to the first interface pin if the first signal from the first driver is received at the second interface pin.

Abstract: A method for detecting the topology of electrical wiring between at least two field-programmable gate arrays (FPGAs) includes implementing a first receive register on a second interface pin; implementing a first send register on a first driver; activating the first driver via a first activation signal; emitting, by the first driver, a first signal, wherein the first signal is defined by the first send register; reading out, by a first receive register, whether the first signal is received at the second interface pin; and allocating the second interface pin to the first interface pin if the first signal from the first driver is received at the second interface pin.

Abstract: A method for determining the power consumption of a programmable logic device, in which at least one configuration parameter is determined in accordance with a predefined configuration and at least one device parameter is determined in accordance with the programmable logic device. The predefined configuration is designed such that the programmable logic device exchanges data with a computing unit through at least one interface pin and receives data from at least one signal source and/or sends it to at least one signal receiver through at least one interface pin. At least one data characteristic of the data exchanged between the computing unit and the programmable logic device as well as at least one signal characteristic of the data received from the at least one signal source and/or sent to the at least one signal receiver are determined.