Patents by Inventor Dominique Delbecq

Dominique Delbecq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180013436
    Abstract: A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.
    Type: Application
    Filed: January 20, 2017
    Publication date: January 11, 2018
    Inventors: Pierre Pascal Savary, Dominique Delbecq, Birama Goumballa
  • Patent number: 9835715
    Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: December 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Dominique Delbecq, Olivier Doare, Gilles Montoriol
  • Publication number: 20170180169
    Abstract: A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value ?1, receive a second phase value ?2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value ?1, and compute a second digital phase shift control value based on the received second phase value ?2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 22, 2017
    Inventors: Olivier Vincent Doare, Dominique Delbecq, Gilles Montoriol
  • Publication number: 20160266239
    Abstract: The embodiments described herein provide a radar device and method that can provide improved sensitivity. In general, the embodiments described herein provide a saturation detector and reset mechanism coupled to a radar receiver. The saturation detector is configured to detect saturation events in the radar receiver, and the reset mechanism is configured to reset at least one filter unit in the radar receiver in response to detected saturation events. As such, the embodiments can facilitate improved radar sensitivity by reducing the effects of saturation events in the radar receiver.
    Type: Application
    Filed: August 19, 2015
    Publication date: September 15, 2016
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, DOMINIQUE DELBECQ, BIRAMA GOUMBALLA
  • Patent number: 9438358
    Abstract: A receiver unit comprising a mixer, a test signal unit, a multiplexer unit, an amplifier unit, a signal strength unit, and a digital control unit is described. The mixer may be arranged to downconvert a received radio-frequency signal to an intermediate frequency, thereby generating a reception signal having the intermediate frequency. The multiplexer unit may be connected to the mixer and to the test signal unit and arranged to select, among the reception signal and a test signal, a multiplexer output signal in dependence on an operating signal. The amplifier unit may be connected to the multiplexer unit and arranged to amplify the multiplexer output signal, thereby generating an amplified signal. The signal strength unit may be connected to the amplifier unit and arranged to generate a signal strength indicator indicative of a signal strength of the amplified signal.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 6, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dominique Delbecq, Fares Jaoude
  • Patent number: 9379721
    Abstract: An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. A main varactor bank has N varactors and a series varactor bank has A varactors, the main varactor bank being connected in series with the series varactor bank. A shunt varactor bank of B varactors may be coupled to a ground reference and connected between the main varactor bank and the series varactor bank. When a varactor is switched in the main varactor bank, it provides an equivalent capacitance step size (or frequency step) smaller than size of a capacitance step when switching a single varactor on or off. According to the number of varactors selected in the shunt varactor, B, this frequency step can be made programmable.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: June 28, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cristian Pavao-Moreira, Dominique Delbecq, Jean-Stephane Vigier
  • Publication number: 20160154092
    Abstract: An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.
    Type: Application
    Filed: May 4, 2015
    Publication date: June 2, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, DOMINIQUE DELBECQ, BIRAMA GOUMBALLA, DIDIER SALLE
  • Publication number: 20160109559
    Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesiser, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
    Type: Application
    Filed: March 17, 2015
    Publication date: April 21, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: DOMINIQUE DELBECQ, OLIVIER DOARE, GILLES MONTORIOL
  • Publication number: 20160103206
    Abstract: A radar device comprises at least one transmitter unit for transmitting a radar signal, at least one receiver unit for receiving a reflected radar signal, and a phase shift unit for producing a phase shift in the frequency modulated radar signal in response to a phase shift signal. The receiver unit comprises at least one filter unit for filtering the received signal and is arranged for resetting the filter unit in response to said phase shift signal, so as to avoid saturation of the filter unit due to the phase shift.
    Type: Application
    Filed: March 9, 2015
    Publication date: April 14, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, DOMINIQUE DELBECQ, BIRAMA GOUMBALLA
  • Patent number: 9306619
    Abstract: A direct-sequence spread spectrum signal receiving device may comprise a receiver unit, a chip sequence generating unit, a correlation unit, and comparison unit. The receiver unit may extract a chip stream from a radio-frequency signal, said chip stream containing a first chip sequence. The chip sequence generating unit may generate a plurality of trial chip sequences on the basis of a first trial chip sequence and on the basis of a plurality of index rotations. The correlation unit may determine a plurality of correlation values on the basis of said plurality of trial chip sequences and on the basis of said first chip sequence, each of said correlation values indicating a degree of correlation between a respective one of said trial chip sequences and said first chip sequence. The comparison unit may determine whether a maximum one of said correlation values exceeds a defined threshold value.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: April 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert Gach, Dominique Delbecq
  • Patent number: 9197403
    Abstract: An electronic device has a calibration arrangement for controlling a frequency characteristic of a PLL circuit having a phase comparator having an output for generating a phase difference signal, a voltage controlled oscillator and a divider. The divisor of the divider is programmable, and the oscillator is also directly modulated by an oscillator modulation signal. A modulation unit has a modulation input for receiving a modulation signal and generates the oscillator modulation signal and the divisor such that modulation generates a predefined change of the output frequency and a change of the divisor proportional to said predefined change. The calibration arrangement receives the phase difference signal, and has a ripple detector for providing a detector output signal by detecting a ripple on the phase difference signal correlated to edges in the modulation signal. A calibration control unit adjusts the oscillator modulation signal based on the detector output signal such that the ripple is reduced.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: November 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Laurent Gauthier, Dominique Delbecq, Jean-Stephane Vigier
  • Publication number: 20150326235
    Abstract: An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. A main varactor bank has N varactors and a series varactor bank has A varactors, the main varactor bank being connected in series with the series varactor bank. A shunt varactor bank of B varactors may be coupled to a ground reference and connected between the main varactor bank and the series varactor bank. When a varactor is switched in the main varactor bank, it provides an equivalent capacitance step size (or frequency step) smaller than size of a capacitance step when switching a single varactor on or off. According to the number of varactors selected in the shunt varactor, B, this frequency step can be made programmable.
    Type: Application
    Filed: July 6, 2012
    Publication date: November 12, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Cristian PAVAO-MOREIRA, Dominique DELBECQ, Jean St├ęphane VIGIER
  • Patent number: 9143190
    Abstract: Methods and receiver circuits are provided for correlating an incoming signal with PN codes. An embodiment of the method includes receiving I/Q baseband samples in the I/Q domain; converting the I/Q baseband samples to phase baseband samples; generating a pseudonoise (PN) code; converting the PN code to PN phase data; performing a correlation on the phase baseband samples using the PN phase data to generate correlated I/Q values; performing an adding operation on the correlated I/Q values to generate demodulated I/Q values; converting the demodulated I/Q values into demodulated phase values; performing a frequency correction operation on the demodulated phase values to generate frequency correction data; converting the demodulated I/Q values into demodulated magnitude values; and performing signal decoding and synchronization on the magnitude values to generate output data. The operation of performing correlation on the phase baseband samples using the PN phase data is accomplished using scalar subtraction.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 22, 2015
    Assignee: FREESCALE SEMICONDUCTOR,INC
    Inventors: James A. Stephens, Dominique Delbecq, Daniel M. Perrine
  • Patent number: 9094084
    Abstract: A signal detector is configured to detect a signal of interest in a received signal. The received signal may comprise noise. The signal of interest is oscillatory at least during one or more time segments. The signal detector comprises a frequency discriminator arranged to determine an instantaneous frequency of the received signal, an evaluator arranged to determine an amount of change of the instantaneous frequency during a test interval, and a comparator arranged to determine whether the amount of change is below a given threshold. The signal of interest may be digitally modulated. In this case the test interval may be shorter than the duration of one data bit in the signal of interest. In a related aspect, a signal transmission system comprises a signal generator for generating a signal of interest and a signal detector for detecting the signal of interest in a received signal. A method of detecting a signal of interest in a received signal is also proposed.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Dominique Delbecq
  • Publication number: 20150207577
    Abstract: A receiver unit comprising a mixer, a test signal unit, a multiplexer unit, an amplifier unit, a signal strength unit, and a digital control unit is described. The mixer may be arranged to downconvert a received radio-frequency signal to an intermediate frequency, thereby generating a reception signal having the intermediate frequency. The multiplexer unit may be connected to the mixer and to the test signal unit and arranged to select, among the reception signal and a test signal, a multiplexer output signal in dependence on an operating signal. The amplifier unit may be connected to the multiplexer unit and arranged to amplify the multiplexer output signal, thereby generating an amplified signal. The signal strength unit may be connected to the amplifier unit and arranged to generate a signal strength indicator indicative of a signal strength of the amplified signal.
    Type: Application
    Filed: September 14, 2012
    Publication date: July 23, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Dominique Delbecq, Fares Jaoude
  • Publication number: 20150146835
    Abstract: An electronic device has a calibration arrangement for controlling a frequency characteristic of a PLL circuit having a phase comparator having an output for generating a phase difference signal, a voltage controlled oscillator and a divider. The divisor of the divider is programmable, and the oscillator is also directly modulated by an oscillator modulation signal. A modulation unit has a modulation input for receiving a modulation signal and generates the oscillator modulation signal and the divisor such that modulation generates a predefined change of the output frequency and a change of the divisor proportional to said predefined change. The calibration arrangement receives the phase difference signal, and has a ripple detector for providing a detector output signal by detecting a ripple on the phase difference signal correlated to edges in the modulation signal. A calibration control unit adjusts the oscillator modulation signal based on the detector output signal such that the ripple is reduced.
    Type: Application
    Filed: July 20, 2012
    Publication date: May 28, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Laurent Gauthier, Dominique Delbecq, Jean St├ęphane Vigier
  • Publication number: 20140254636
    Abstract: Methods and receiver circuits are provided for correlating an incoming signal with PN codes. An embodiment of the method includes receiving I/Q baseband samples in the I/Q domain; converting the I/Q baseband samples to phase baseband samples; generating a pseudonoise (PN) code; converting the PN code to PN phase data; performing a correlation on the phase baseband samples using the PN phase data to generate correlated I/Q values; performing an adding operation on the correlated I/Q values to generate demodulated I/Q values; converting the demodulated I/Q values into demodulated phase values; performing a frequency correction operation on the demodulated phase values to generate frequency correction data; converting the demodulated I/Q values into demodulated magnitude values; and performing signal decoding and synchronization on the magnitude values to generate output data. The operation of performing correlation on the phase baseband samples using the PN phase data is accomplished using scalar subtraction.
    Type: Application
    Filed: June 12, 2013
    Publication date: September 11, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: James A. Stephens, Dominique Delbecq, Daniel M. Perrine
  • Publication number: 20140254637
    Abstract: A direct-sequence spread spectrum signal receiving device may comprise a receiver unit, a chip sequence generating unit, a correlation unit, and comparison unit. The receiver unit may extract a chip stream from a radio-frequency signal, said chip stream containing a first chip sequence. The chip sequence generating unit may generate a plurality of trial chip sequences on the basis of a first trial chip sequence and on the basis of a plurality of index rotations. The correlation unit may determine a plurality of correlation values on the basis of said plurality of trial chip sequences and on the basis of said first chip sequence, each of said correlation values indicating a degree of correlation between a respective one of said trial chip sequences and said first chip sequence. The comparison unit may determine whether a maximum one of said correlation values exceeds a defined threshold value.
    Type: Application
    Filed: November 16, 2011
    Publication date: September 11, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Robert Gach, Dominique Delbecq
  • Publication number: 20120307877
    Abstract: A signal detector is configured to detect a signal of interest in a received signal. The received signal may comprise noise. The signal of interest is oscillatory at least during one or more time segments. The signal detector comprises a frequency discriminator arranged to determine an instantaneous frequency of the received signal, an evaluator arranged to determine an amount of change of the instantaneous frequency during a test interval, and a comparator arranged to determine whether the amount of change is below a given threshold. The signal of interest may be digitally modulated. In this case the test interval may be shorter than the duration of one data bit in the signal of interest. In a related aspect, a signal transmission system comprises a signal generator for generating a signal of interest and a signal detector for detecting the signal of interest in a received signal. A method of detecting a signal of interest in a received signal is also proposed.
    Type: Application
    Filed: February 16, 2010
    Publication date: December 6, 2012
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Dominique Delbecq
  • Patent number: 8183941
    Abstract: An electronic device (ED) is intended for generating a local oscillator signal having a chosen frequency FLO from a main signal outputted by a voltage-controlled oscillator (VCO) and having a fundamental frequency FVCO and harmonics thereof. This electronic device (ED) comprises a frequency division means (D1, D2) arranged to divide the frequency of a signal by a chosen factor N and a filter means (F1, F2) arranged to select a chosen Mth order harmonic of a signal, these frequency division means (D1, D2; D) and filter means (F1, F2) being arranged to process the main signal in common to output the local oscillator signal with a chosen frequency FLO equal to MxFVCO/N.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: May 22, 2012
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Dominique Delbecq, Michel Germe