Patents by Inventor Don Choi
Don Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154042Abstract: A semiconductor device includes a substrate including an upper surface and a lower surface that are opposite to each other in a first direction, an active pattern which is on the upper surface of the substrate and extends in a second direction, a gate electrode which is on the active pattern and extends in a third direction, a first source/drain pattern which is connected to the active pattern on the upper surface of the substrate, and includes a lower epitaxial region and an upper epitaxial region, the upper epitaxial region including an epitaxial recess, and the lower epitaxial region being inside the epitaxial recess, a first source/drain contact, which is connected to the first source/drain pattern and extends into the substrate, and a contact silicide layer, which is between the first source/drain contact and the first source/drain pattern and contacts the lower epitaxial region.Type: ApplicationFiled: July 17, 2023Publication date: May 9, 2024Inventors: Jun Ki PARK, Wan Don KIM, Jeong Hyuk YIM, Hyo Seok CHOI, Sung Hwan KIM
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Publication number: 20240120279Abstract: A semiconductor device may include a first film and a second film defining parts of a trench, a plug conductive film, a via, and a wiring in the trench. The trench may include a second sub-trench having a second width below a first sub-trench having a first width. The plug conductive film may extend from a first side of the first film to penetrate a bottom face of the trench. An uppermost face of the plug conducive film may be in the trench. The via may include an insulating liner between the plug conductive film and the first film. The uppermost face of the plug conductive film and at least a part of a side wall of the plug conductive film may be in contact with the wiring. An upper face of the insulating liner may be exposed by a bottom face of the second sub-trench.Type: ApplicationFiled: September 21, 2023Publication date: April 11, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong Hyuk YIM, Wan Don KIM, Hyun Bae LEE, Hyo Seok CHOI, Geun Woo KIM
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Publication number: 20240021259Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: ApplicationFiled: July 28, 2023Publication date: January 18, 2024Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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INDUCTIVELY COUPLED PLASMA APPARATUS FOR EXHAUST GAS TREATMENT AND IMPEDANCE MATCHING METHOD THEREOF
Publication number: 20230377842Abstract: An inductively coupled plasma apparatus for exhaust gas treatment, includes: an inductively coupled plasma reactor installed on an exhaust pipe through which exhaust gas generated from a process chamber of a semiconductor manufacturing facility is discharged; a power supply configured to supply high-frequency power to the inductively coupled plasma reactor through a transmission line; and an impedance matching unit configured to match impedance of the inductively coupled plasma reactor with impedance of the power supply, wherein the impedance matching unit includes a variable power storage element, an operation data measuring instrument measuring operation data of the inductively coupled plasma reactor, and a controller stepwise adjusting total capacitance by the variable power storage element using an operation data sampling value obtained by the operation data measuring instrument in one operation cycle and reflecting the adjusted total capacitance on starting impedance matching in a next operation cycle.Type: ApplicationFiled: February 9, 2022Publication date: November 23, 2023Applicant: LOT CES CO., LTD.Inventors: Jin Ho BAE, Min Jae KIM, Sang Don CHOI -
Publication number: 20230298645Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Hyeok Jun CHOI, Young Chul CHO, Seung Jin PARK, Jae Woo PARK, Young Don CHOI, Jung Hwan CHOI
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Publication number: 20230298639Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: ApplicationFiled: May 25, 2023Publication date: September 21, 2023Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 11742040Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: March 25, 2022Date of Patent: August 29, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Patent number: 11705166Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.Type: GrantFiled: February 23, 2021Date of Patent: July 18, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Patent number: 11682436Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.Type: GrantFiled: July 14, 2021Date of Patent: June 20, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeok Jun Choi, Young Chul Cho, Seung Jin Park, Jae Woo Park, Young Don Choi, Jung Hwan Choi
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Publication number: 20230143365Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.Type: ApplicationFiled: June 29, 2022Publication date: May 11, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Joo Hwan KIM, Jun Young PARK, Jin Do BYUN, Kwang Seob SHIN, Eun Seok SHIN, Hyun-Yoon CHO, Young Don CHOI, Jung Hwan CHOI
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Publication number: 20230138845Abstract: A memory device, a host device and a method of operating the memory device are provided. The memory device includes a data signal generator configured to provide a data signal to a transmission driver, the transmission driver configured to output a multi-level signal having any one of first to third signal levels based on the data signal, a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal, a data signal controller configured to adjust the data signal based on a decoding result of the command decoder, and a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder.Type: ApplicationFiled: July 6, 2022Publication date: May 4, 2023Inventors: Joo Hwan KIM, Su Cheol LEE, Jin Do BYUN, Eun Seok SHIN, Young Don CHOI, Jung Hwan CHOI
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Publication number: 20230069876Abstract: In accordance with an embodiment, a noise reduction device includes a housing; and a slit located inside the housing and having a unit cell located therein, the unit cell comprising a sound absorbing layer configured to absorb noise generated from a sound source inside the housing, and a meta-material panel layer located on one surface of the sound absorbing layer, the meta-material panel layer comprising a sound meta-material.Type: ApplicationFiled: August 31, 2022Publication date: March 9, 2023Inventors: Jin Ho Hwang, Ji Ah Kim, Min Ho Cho, Byoung Chul Park, Young Hwan Yoon, Kang Ho Cheon, Eun Gook Kim, Young Don Choi, Jin Woo Lee
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Patent number: 11600539Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.Type: GrantFiled: June 23, 2021Date of Patent: March 7, 2023Inventors: Min-Jae Lee, Sang-Lok Kim, Byung-Hoon Jeong, Tae-Sung Lee, Jeong-Don Ihm, Jae-Yong Jeong, Young-Don Choi
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Patent number: 11461176Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.Type: GrantFiled: August 10, 2021Date of Patent: October 4, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Young Park, Young-Hoon Son, Hyun-Yoon Cho, Young Don Choi, Jung Hwan Choi
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Publication number: 20220278284Abstract: Provided herein are an organic electronic compound capable of improving luminous efficiency, stability and lifespan of an electronic device, an organic electronic element employing the same, and an electronic device thereof.Type: ApplicationFiled: December 3, 2021Publication date: September 1, 2022Applicant: DUK SAN NEOLUX CO., LTD.Inventors: Ki Ho SO, Sang Don CHOI, Sun Hee LEE, Won Sam KIM, Soung Yun MUN, Jung Wook LEE, Hyung Dong LEE
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Publication number: 20220215892Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Inventors: Eun-ji KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 11342038Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.Type: GrantFiled: January 29, 2021Date of Patent: May 24, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
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Publication number: 20220157845Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.Type: ApplicationFiled: July 26, 2021Publication date: May 19, 2022Inventors: MIN JAE LEE, Jin Do Byun, Young-Hoon Son, Young Don Choi, Pan Suk Kwak, Myung Hun Lee, Jung Hwan Choi
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Publication number: 20220148634Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.Type: ApplicationFiled: July 14, 2021Publication date: May 12, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Hyeok Jun CHOI, Young Chul CHO, Seung Jin PARK, Jae Woo PARK, Young Don CHOI, Jung Hwan CHOI
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Patent number: RE49206Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.Type: GrantFiled: November 22, 2019Date of Patent: September 6, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Woon Kang, Jeong-don Ihm, Byung-Hoon Jeong, Young-Don Choi