Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

Abstract: An electrode assembly, a rechargeable battery comprising the same, and a method for manufacturing the rechargeable battery are provided. The electrode assembly comprises an electrode stack in which a plurality of electrodes and a plurality of separators are alternately combined. The electrode assembly also comprises an electrode tab part including a plurality of electrode tabs respectively connected to the plurality of electrodes to extend from a side surface of the electrode stack. The electrode tab part comprises an inclined portion provided on a first side thereof and a tab collection portion provided on a second side thereof, the inclined portion extends from the side surface of the electrode stack and bent in a direction, in which the plurality of electrode tabs are collected, and the tab collection portion extends from the inclined portion and has a shape in which the plurality of electrode tabs are joined.

Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

Abstract: The present invention describes a component for a secondary battery and a manufacturing method thereof, and a secondary battery manufactured by using the component. The component for a secondary battery according to the present invention comprises a lead-free soldering bridge having a melting point of 150 to 300° C. and containing tin (Sn) and copper (Cu) as a main ingredient; the first and second metal plates spaced therebetween through a gap and coupling with the lead-free soldering bridge. According to the present invention, when an over-current flows through the component for a secondary battery, the temperature of the lead-free soldering bridge is locally increased rapidly to melt the lead-free soldering bridge, thereby efficiently interrupting the flow of an over-current.

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Abstract: A battery pack comprises first and second battery cells stacked in a vertical direction and a safety device that connects a first electrode lead provided in the first battery cell to a second electrode lead provided in the second battery cell to allow current to flow therebetween or separates the first electrode lead and the second electrode lead from each other to break the current when the first and/or second battery cells swell due to overcharging and/or overcurrent. In particular, the safety device comprises a connection member that electrically connects the first and second electrode leads to each other and a movable member that linearly moves the connection member when the first and second battery cells swell and separates the first electrode lead and the second electrode lead from each other, thereby breaking the current.

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

Abstract: A two-layer thermal container according to the present invention comprises an outer container having a first intake port at an upper end thereof and an opening at a lower portion thereof; an inner container as a cylindrical body having a second intake port formed at an upper end thereof and inserted into an opening of the outer container with the outer circumferential surface of the second intake port being in close contact with the inner circumferential surface of the first intake port; a sealing member assembled to the opening to seal the opening and having its upper surface contacted with the bottom surface of the inner container; and an insertion stopper inserted into the second intake port of the inner container to seal the second intake port.

Abstract: Provided are an anode for a secondary battery including an anode collector, an anode active material coated on the anode collector, and a non-coating portion (anode tab) which protrudes from one side of the anode collector and is not coated with an anode active material, wherein the anode includes a metal member which is bonded to the non-coating portion and has higher reactivity or reducibility with respect to a metal oxide than the anode collector, and a secondary battery including the anode.

Abstract: Disclosed is a manganese-based lithium secondary battery comprising a cathode containing manganese-based lithium metal oxide, an anode, and an electrolyte, wherein the anode comprises an anode active material in which a Mn scavenger capable of reducing manganese ions on a surface by conducting or semiconducting properties is coated on part or all of anode active material particles. Through the use of the Mn scavenger, manganese ion dissolved from the manganese-based cathode active material into the electrolyte is preferentially deposited on the Mn scavenger coated on the surface of the anode active material particles, such that the dissolved manganese ion is inhibited from being deposited directly on the surface of the anode active material, and a decomposition of the electrolyte with the deposited manganese component is inhibited. Accordingly, the use of the Mn scavenger can provide a manganese-based lithium secondary battery having excellent storage performance.

Abstract: Provided is a pouch-type secondary battery comprising an electrode assembly equipped with an electrode tab, an electrode lead connected to the electrode tab, a pouch housing accommodating and sealing the electrode assembly such that the electrode lead is exposed partly and equipped with a sealing zone at the edge thereof, a first sealant interposed between the top surface of the electrode lead and the inner surface of the pouch housing and a second sealant interposed between the lower surface of the electrode lead and the inner surface of the pouch housing, wherein the electrode lead includes a joint portion joined to the electrode tab, a terminal portion exposed to the outside of the pouch housing and a fuse portion between the joint portion and the terminal portion, the fuse portion includes a separating groove separated from the sealing zone toward the joint portion and including at least a horizontal slit which is in parallel to the width direction of the electrode lead and a breaking portion disposed mor

Abstract: The present disclosure provides an electrode lead that ensures safety of a secondary battery when gas is generated within the secondary battery. The electrode lead is included in a pouch-type secondary battery in which outer circumferential parts of a pouch casing are sealed and an electrode assembly is accommodated in a center part of the pouch casing.

Abstract: Provided is a pouch-type secondary battery that includes an electrode assembly equipped with an electrode tab, an electrode lead connected to the electrode tab, a pouch housing accommodating and sealing the electrode assembly such that the electrode lead is partially exposed, and first and second sealants within the pouch housing. The electrode lead includes a joint portion joined to the electrode tab, a terminal portion exposed to an outside of the pouch housing and a fuse portion between the joint portion and the terminal portion. The fuse portion includes a separating groove and a breaking portion connected to the separating groove for separating the terminal portion from the joint portion. The first sealant and the second sealant have shapes that are different from each other such that, when the pressure inside the secondary battery is increased, a stress applied to the pouch housing causes the breaking portion to break.