Abstract: A golf club shaft is designed to be strong, light-weighted and flexible and to fit individual custom needs. The shaft is made of both graphite and steel. The inner layer of the golf club shaft could be steel or graphite, outer layer of the golf club shaft also could be steel or graphite, any portion of the shaft could be made of steel only or graphite only, and/or the ratio to the graphite and steel could vary depending on the need of the golfers. Steel layer could be made of coiled steel wire springs.

Abstract: A golf club head with diaphragm which divides the cavity of the golf club head and designed to increase the rebounding force of the golf club head face when it returns to its original shape after being deformed so that golfers can hit the ball farther and accurately. The diaphragm can be just one or indefinite numbers, the shape of diaphragms can be flat, concave, convex, bell-shaped or irregular, the diaphragms can have one or indefinite number of hole(s) in it and/or various gases, compound gases or liquids can be put in the cavity of the golf club head or space between the inner wall of the golf club head face and the diaphragm.

Abstract: An apparatus and method for recognizing a code from a code image that is expressed physically or electronically and extracting data represented in the code image is provided. The method includes the steps of receiving a raw image in which a code image is contained, detecting a background image included in the raw image, extracting a code image region in which a background image is excluded, recognizing the shape and type of the code image and the color or shade represented in each of cells, converting the color or shade recognized from each of the cells into a corresponding character, number, or symbol and generating code data. The code image in which predetermined data are represented as colors or shades are received, and original colors or shades can be precisely discriminated regardless of an environment in which the code image is recognized.

Abstract: A method and a device of consistency buffer for a high performance 3D graphic accelerator is disclosed to retain consistency without detecting any overlapping region in advance but determining an overlapping with respect to a rendered pixel.

Abstract: An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.

Abstract: A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

Abstract: A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about ⅓ in comparison to the existing pipelined divider.

Abstract: A 3D graphic accelerator and a method for processing a graphic acceleration using the same is provided in which the inputted primitives are geometrically processed, and existence of any transparent primitives or dominance/rarity of opaque primitives is determined among the geometrically processed primitives. The primitives are rendered in an object-order style and an image-order style in accordance with the determination. The information on the rendered primitives is stored in a corresponding frame buffer and a bucket, and the rendered primitives are display-refreshed. Thus, the 3D graphic accelerator with order- independent transparency and high performance is obtained.

Abstract: A cache memory system reduces the rate of cache misses. The cache memory system includes a first auxiliary storage device which stores first information blocks and a second auxiliary storage device which stores second information blocks fetched from a lower level memory device. Each second block includes a plurality of the first information blocks. A process for fetching information selectively fetches a first or second information block from the lower level memory device and selectively stores the fetched block in the first auxiliary storage device and/or the second auxiliary storage device. Selection of the size of block to fetch and where to store the fetched block is according to whether the data to be referenced by the central controller is in the first auxiliary storage device or the second auxiliary storage device and whether first information blocks that do not include the referenced data are both in the second information block including the referenced data and in the first auxiliary storage device.

Abstract: A method and apparatus for processing pixel rasterization in a 3D rendering processor is disclosed. According to the method and apparatus, the primary depth checking is performed before the performing of the texture mapping, and thus the unnecessary performing of the texture mapping can be removed. Also, the consistency problem can be simply and easily solved using the flag memory, and by performing the depth reading and depth checking twice, the hit rate of the pixel cache memory is heightened. Thus, the method and apparatus is effective in cost, performance, and power consumption.

Abstract: A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.

Abstract: A method of and a circuit for instruction/data prefetching using a non-referenced prefetch cache, adapted to store instruction/data blocks prefetched in accordance with a variety of existing prefetchinig machanisms, but not referenced by the central processing unit in an on-chip memory as the non-referenced prefetch cache without discarding them when they are replaced by new ones in a prefetch buffer so that a direct memory reference to the non-referenced prefetch instruction/data blocks can be achieved when they are to be referenced at later times, without any requirement of fetching or prefetching them from the lower memory again. Accordingly, it is possible to not only decrease the number of cache misses and the memory latency due to the fetching of instructions/data from the lower memory for the reference to the instructions/data, but also to reduce memory traffic.

Abstract: An apparatus and a method for performing rounding and addition in parallel in a floating point multiplier are disclosed, in which operation time and the size of a chip can be reduced.

Abstract: A method for storing parity and rebuilding the data contents of two failed disks in an external storage subsystem comprises the steps of: proving a disk array defined as a matrix of (N-1).sup.

Abstract: A disk drive constructed according to an exemplary embodiment of the present invention includes a disk having a plurality of tracks formed concentrically along a first surface of the disk for storing data. The tracks are divided into first and second data storage regions positioned between an innermost circumferential region and an outermost circumferential region of the disk. First and second heads write and read data to and from the first surface of the disk. The first head is positioned to access the first data storage region while the second head is positioned to access the second data storage region, and the first head being positioned to access the second data storage region while the second head is positioned to access the first data storage region. First and second arm assemblies are respectively connected to the first and second heads. The first arm assembly extends the first head over a first radius of the disk, and the second arm assembly extends the second head over a second radius of the disk.