Abstract: Apparatus for measuring the noise parameters of a device under test (DUT), with full compensation for impedance mismatches between the DUT and the test apparatus. The apparatus includes an S-parameter measuring device, such as vector network analyzer (VNA), combined with a noise module. The noise module includes, among other things, a pair of test ports for the DUT, a noise source which can be turned on or off by an external controller, a receiver, and a switch for coupling the output of the DUT to selectably either the receiver or port 2 of the VNA.

Abstract: A full reversing millimeter test set comprising a pair of test head assemblies which are connected to an analyzer by means of coaxial cables enclosed within a sheath. Microwave signals are sent to the test head assemblies and therein frequency-multiplied so as to provide the necessary millimeter test signals required for testing microwave devices in the W band of 75-110 GHz. By placing the millimeter wave components in the test head assemblies, the phase distortions which would otherwise be encountered in flexing or movement of the interconnecting coaxial cables and the bulk, signal loss and phase distortions associated with long waveguide are eliminated.

Abstract: An electronic circuit is provided for protecting an electronic system and its power supply from damages caused by an over-current condition. The circuit automatically enters into a first state upon application of power from the power supply. In this first state, current is allowed to pass from the power supply through a channel to the electronic system. Upon detecting an over-current condition, a positive feedback will cause the circuit to enter into a second state, wherein the channel is cutoff.

Abstract: A dual modulus fractional divider having a dual modulus prescaler coupled to a programmable divider. Latches and a full adder are provided for programming the programming divider with a modulus A, a modulus B, a modulus (A-1) and a modulus (B+1). A rate multiplier controls the adder to provide the desired resolution of the divider.

Abstract: A switching power supply with an injection signal frequency locking circuit is described comprising a switched transformer controlled by a pulse width modulator. The pulse width modulator output is in turn controlled by an error signal form the output of the power supply such that as the potential on the output of the power supply increases, the duration of the pulses on the output of the pulse width modulator decreases; and conversely, as the potential on the output of the power supply decreases, the pulse duration on the output of the pulse width modulator increases. The increasing and decreasing of the pulse duration on the output of the pulse width modulator controls the length of time that a potential is applied across the primary of the transformer so as to hold the potential on the output of the power supply to a predetermined value. The frequency of the oscillator is fixed by choosing the free-running frequency of the oscillator to be slightly less than a desired fixed predetermined frequency.

Abstract: An addressable signalling apparatus wherein a shift register may be sequentially advanced through units of address by inputs to an OR gate. Such inputs may come from programmable connectors connected to selected input terminals defining a unique address or from one designated connector which is connected as an input to each of said OR gates defining an address unit substitute. The OR gates are connected in turn to a shift register which, when it sequentially shifts through programmed units of address, activates an output means. Once the output is enabled, a multiplicity of output messages may be transmitted through the apparatus.The apparatus includes a logic circuit for resetting the shift means in the event an input not corresponding either to the programmed units of address or the common designated substitute address unit is received.

Abstract: An addressable signalling apparatus wherein a shift register may be sequentially advanced through units of address by inputs to an OR gate. Such inputs may come from programmable connectors connected to selected input terminals defining a unique address or from one designated connector which is connected as an input to each of said OR gates defining an address unit substitute. The OR gates are connected in turn to a shift register which, when it sequentially shifts through programmed units of address, activates an output means. Once the output is enabled, a multiplicity of output messages may be transmitted through the apparatus.The apparatus includes a logic circuit for resetting the shift means in the event an input not corresponding either to the programmed units of address or the common designated substitute address unit is received.