Abstract: A digital system is provided that includes a central processing unit (CPU) that has an instruction execution pipeline with a plurality of functional units for executing instructions in a sequence of CPU cycles. The execution units are clustered into two or more groups. Cross-path circuitry is provided such that results from any execution unit in one execution unit cluster can be supplied to execution units in another cluster. A cross-path stall is conditionally inserted to stall all of the functional groups when one execution unit cluster requires an operand from another cluster on a given CPU cycle and the execution unit that is producing that operand completes the computation of that operand on an immediately preceding CPU cycle.

Abstract: A method for processing data is provided that includes storing a write operation in a store buffer that indicates a first data element is to be written to a memory array element. The write operation includes a first address associated with a location in the memory array element to where the first data element is to be written. A read operation may be received at the store buffer, indicating that a second data element is to be read from the memory array element. The read operation includes a second address associated with a location in the memory array element from where the second data element is to be read. A hashing operation may be executed on the first and second addresses such that first and second hashed addresses are respectively produced. The hashed addresses are compared. If they match, the first data element is written to the memory array element before the read operation is executed.

Abstract: A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.

Abstract: A single-event-upset, fault-tolerant data processor architecture enables error detection and correction according to algorithms given. A hardware intensive solution compares signatures of two passes through a block of instructions. A match of signatures generated from the two passes through the block of instructions indicates valid operations, a mismatch indicates an error. A software assisted solution compares a signature generated from one pass through a block of instructions with a signature pre-calculated by a compiler or with a one of a set of pre-calculated signature selected at run time. This is useful for digital signal processor design using deep-sub-micron devices and dynamic logic for superior system performance by enabling detection of errors that can result from the low noise-immunity in circuits using higher impedance smaller devices with low threshold voltage and dynamic logic.

Abstract: A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.

Abstract: A data processing system (1300) is provided with a digital signal processor (DSP) (1301) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (.D1, .D2) connected to dual memory ports (T1, T2) in a level one data cache memory controller (1720a). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.

Abstract: This invention is memory system including plural memory banks logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a first predetermined set of address bits. A second decoder selectively powers one of the X rows corresponding to a second predetermined set of address bits. Multiplexers select the powered memory bank for data access. Thus one of the plural memory banks is powered and selected for memory access corresponding to the first and second predetermined sets of bits of the received address. This memory system is preferably a cache memory including a further column of memory banks for cache addresses and cache control data including at least a cache valid tag. A multiplexer selects one row corresponding to the second predetermined set of address bits.

Abstract: A computer system (10). The computer system comprises processing circuitry (14) and storage circuitry (24) for storing a plurality of files. The plurality of files include a circuit description file (243) comprising data describing devices and signals in a circuit. The plurality of files also include a plurality of list expressions (244) relating to one of devices, signals, or devices and signals described by the data in the circuit description. Still further, the plurality of files also include a plurality of rules (245). The processing circuitry is programmed to perform various steps. These steps include processing (34) the plurality of list expressions to extract a plurality of lists in response to the circuit description. Each of the plurality of lists comprises a non-negative integer number of elements.

Abstract: A circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a plurality of N-type transistors coupled to the storage circuit. The write circuit is operable to write a data bit to the first and second storage capacitors. The power-off state storage circuit also has a sense amplifier connected to the storage circuit and that is operable to read the data bit stored by the storage capacitors. The first and second capacitors in the storage circuit are electrically isolated from the positive power supply such that when the positive power supply is terminated any charge stored on the first and second capacitors is prevented from discharging to the terminated power supply.

Abstract: A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.

Abstract: A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.

Abstract: A single-chip multiprocessor (2, 102) is disclosed. The multiprocessor (2, 102) includes multiple central processing units, or CPUs, (10, 110) that share a floating-point unit (5, 105). The floating-point unit (5, 105) may receive floating-point instruction codes from either or both of the multiple CPUs (10, 110) in the multiprocessor (2, 102), and includes circuitry (52) for decoding the floating-point instructions for execution by its execution circuitry (65). A dispatch unit (56) in the floating-point unit (5, 105) performs arbitration between floating-point instructions if more than one of the CPUs (10, 110) is forwarding instructions to the floating-point unit (5, 105) at the same time. Dedicated register banks, preferably in the form of stacks (60), are provided in the floating-point unit (5, 105).

Abstract: In a method embodiment (10), the method operates a microprocessor (110), and the microprocessor has an instruction set. The method first (11) stores an identifier code uniquely identifying the particular microprocessor in a one-time programmable register. The method second (12) issues to the microprocessor an identifier request instruction from the instruction set. The method then, and in response to the identifier request instruction, provides (18) from the microprocessor an identifier code. Other circuits, systems, and methods are also disclosed and claimed.

Abstract: A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The diagnostic evaluations include a first evaluation to occur under non-failure operation at a first clock period (24) and a last evaluation to occur under non-failure operation at a last clock period (26). The microprocessor further includes circuitry (14) for issuing a series of addresses to the readable memory in order to address the code for performing diagnostic evaluations of the microprocessor. Still further, the microprocessor includes a conductor (D0) externally accessible and for providing a signal from the microprocessor. Lastly, the microprocessor includes circuitry (12) for outputting a diagnostic signal on the externally accessible conductor during performance of the diagnostic evaluations.

Abstract: A microprocessor (10) and system (2) are disclosed, in which capability for the detection and handling of modifications of instructions potentially in the pipeline is implemented. The microprocessor (10) includes a self-modifying code (SMC) unit (50) that includes a fetch address window maintenance unit (52), a write comparator (54) associated with each load/store unit (40) in the microprocessor (10) that performs writebacks to memory (16, 11, 5), and a shared write comparator (55). The fetch address window maintenance unit (52) includes a minimum latch (60) that stores the lowest fetch address since a pipeline flush or machine reset, and a maximum latch (62) that stores the highest fetch address since flush or reset, and updates the minimum and maximum latches (60, 62) upon detecting that the current fetch address (LASTFA) falls outside of the current window.

Abstract: A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines (34) whether the received instruction is preceded by an instruction path leading code. Third, the method passes (36 or 38) the received instruction along at least one instruction path in a plurality of instruction paths. Fourth, in response to determining that the received instruction is preceded by an instruction path leading code, the method executes a machine word corresponding to the received instruction and selected from one of the plurality of instruction paths. Specifically, the selected instruction path is selected in response to the instruction path leading code.

Abstract: A microprocessor (10) and system (2) including a multi-stream pipeline unit (25) are disclosed. The multi-stream pipeline unit (25) includes individual fetch units (26), instruction caches (16.sub.i), and decoders (34) in separate instruction streams (PROC0, PROC1) or pipelines. A common scheduler (36) is provided to check for dependencies among the instructions from the multiple instruction streams (PROC0, PROC1), and to launch instructions for execution by the various execution units (31, 40, 42, 50), including a microcode unit (47). A common register file (39) includes register banks (70) dedicated to each pipeline, and also a register bank (72) that includes temporary and shared registers available to instructions of either instruction stream (PROC0, PROC1), such as useful in the event of register renaming due to a dependency. Each decoded instruction in the scheduler (36) has an identifier (PROC) indicating the one of the instruction streams (PROC0, PROC1) from which it was issued.

Abstract: A microprocessor includes a control register having a predetermined bit which is unconditionally writable to either a first state or a second state. Additional bits of the control register are writable to either the first or second state when the predetermined bit has the first state. Each additional bit is not writable when the predetermined bit has the second state. The microprocessor further includes at least one circuit controlled by the state of a corresponding one of the additional bits of the control register. The writability of the additional bits is preferably further conditioned upon the state of a machine status register, which is unconditionally writable to either the first state or the second state. A primary AND gate and a secondary AND gate corresponding to each additional bit control the writability of the additional bits.

Abstract: A microprocessor of the superscalar pipelined type, having speculative execution capability, is disclosed. Speculative execution is under the control of a fetch unit having a branch target buffer and a return address stack, each having multiple entries. Each entry includes an address value corresponding to the destination of a branching instruction, and an associated register value, such as a stack pointer. Upon the execution of a subroutine call, the return address and current stack pointer value are stored in the return address stack, to allow for fetching and speculative execution of the sequential instructions following the call in the calling program. Any branching instruction, such as the call, return, or conditional branch, will have an entry included in the branch target buffer; upon fetch of the branch on later passes, speculative execution from the target address can begin using the stack pointer value stored speculatively in the branch target buffer in association with the target address.

Abstract: A virtual field programmable gate array device (20) includes a plurality of processors (22), each containing a central processing unit (24), memory (34), and a network interface (26). Each processor (22) may be programmed to emulate a multiple number of gates of a conventional field programmable gate array device. Each processor (22) is part of a network array to allow for information transfer between and among each processor (22). Information transfer is accomplished through the use of delivery units (50) that identify the routing vector for the information to an appropriate processor (22).