Abstract: A microprocessor (5) having at least one arithmetic logic unit, or ALU, (42) for operating upon operands of multiple number representation types is disclosed. The ALU (42) includes a binary logical unit (52) for performing logical operations upon operands in a binary representation, and an arithmetic unit (50, 50') for performing arithmetic operations upon operands in a redundant number representation. The redundant number representation is of a type that may be operated upon by adder circuitry such as signed-digit adders or carry-save adders, where carry information need not propagate along the entire operand. A register file (39, 39') is provided, which stores each operand in both the binary form and in the redundant number representation; a valid bit (V) is provided in combination with the binary portion of each entry in the register file (39, 39').

Abstract: Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.