Patents by Inventor Donald Eric Thompson

Donald Eric Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230198209
    Abstract: An improved method and structure for forming an electrical interconnects mechanism in a Power Distribution Network (PDN) by placing capacitors on the top of the pin array on the printed circuit board (PCB) of the structure to decouple the PDN and results in lower impedance benefitting the frequency range of the PDN effecting a significant performance improvement in the spring-pin inductance from the transmission line. This reduction in impedance reduces the power supply ripple.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 22, 2023
    Inventor: Donald Eric Thompson
  • Publication number: 20230180397
    Abstract: The present invention provides a novel method of constructing a coax spring-pin socket that furnishes better performance and is easier to manufacture in volume using common dielectrics and copper plating. This is accomplished by, in application, a lamination of PCB dielectric layers. This dielectric block is then drilled, plated, etched, and drilled in steps for the construction of a coaxial structure for the signal pins, and a ground structure for ground pins. This design process that can be quickly adjusted and customized for each design.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Applicant: R&D Circuits
    Inventor: Donald Eric Thompson
  • Publication number: 20230026067
    Abstract: The present invention provides a method for detecting and adjusting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. This is accomplished, by after detecting poor back drills in a PCB, measuring the actual thickness of each PCB board. Next, the measured actual thickness of each PCB board is compared with .the theoretical thickness of each PCB board. The back drill depth for each area of the PCB board is then adjusted for its theoretical thickness and percent variation from the measured thickness.to adjust the poor back drill.
    Type: Application
    Filed: July 21, 2021
    Publication date: January 26, 2023
    Inventors: Michael Caprio, Dwarkesh Patel, Hiren Patel, Yubing Wong, Donald Eric Thompson
  • Publication number: 20220252660
    Abstract: The present invention provides a method for detecting failed back-drills in PCBs in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired. The present invention accomplishes this by adding a short to ground connection for every back-drill via that will be cut when the back-drill removes the via stub. If the back-drill is bad or failed the short to ground will fail the subsequent electrical tests. The PCB can be repaired by re-drilling the hole or via. The present invention allows for detecting failed back-drills with easy detection in the manufacturing stage using standard equipment and test procedures. This process creates a simple pass-fail measurement that uses an existing common test process to catch failed back drills in the PCB fabrication facility. This allows for easy and cost-effective repair and guarantees back-drill failures do not pass into the field.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 11, 2022
    Applicant: R & D Circuits, Inc.
    Inventors: Donald Eric Thompson, Thomas Smith
  • Publication number: 20210376535
    Abstract: The present invention provides for an improved method and structure for forming an electrical interconnects mechanism in a Power Distribution Network (PDN) by placing capacitors on the top of the pin array on the printed circuit board (PCB) of the structure to decouple the PDN and results in lower impedance benefitting the frequency range of the PDN effecting a significant performance improvement in the spring-pin inductance from the transmission line. This reduction in impedance reduces the power supply ripple.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventor: Donald Eric Thompson
  • Publication number: 20190141840
    Abstract: A method and structure that forms a PCB while removing or eliminating a stub from a via without back-drilling or doing multi-laminations. In the preferred embodiment, the printed circuit board includes a via extending through a plurality of stacked layers. The via includes a plated through hole that is connected to at least two other metalized layers. There is a portion of the via that is extraneous and that has a negative performance on the functionality of the printed circuit board. The single lamination buried via method adds a seed layer resist that prevents an electrical connection during electroplating thus preventing the via from metalizing where it is not desired.
    Type: Application
    Filed: August 1, 2018
    Publication date: May 9, 2019
    Inventors: Donald Eric Thompson, Dhananjaya Turpuseema
  • Publication number: 20120142200
    Abstract: A receptacle connector of the present invention is used as an electrical connector configured to connect two circuit boards. The receptacle connector includes: a housing in which a receiving space is formed, a connection target being inserted in the receiving space; a plurality of contacts being arranged parallel to one another, having a plurality of signal line contacts and a plurality of ground contacts, and being placed with every two adjacent signal line contacts for transmitting signals interposed between two ground contacts; a supporting member made of an electrically-insulating synthetic resin material, and configured to integrally support and fix thereto the plurality of contacts; and a common contact made of a conductive resin material and configured to electrically connect the plurality of ground contacts together among the plurality of contacts. The plurality of contacts integrated together by the supporting member are received in the receiving space.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Inventors: Toshiyasu ITO, Donald Eric Thompson, Takeshi Nishimura
  • Patent number: 8177564
    Abstract: A receptacle connector of the present invention is used as an electrical connector configured to connect two circuit boards. The receptacle connector includes: a housing in which a receiving space is formed, a connection target being inserted in the receiving space; a plurality of contacts being arranged parallel to one another, having a plurality of signal line contacts and a plurality of ground contacts, and being placed with every two adjacent signal line contacts for transmitting signals interposed between two ground contacts; a supporting member made of an electrically-insulating synthetic resin material, and configured to integrally support and fix thereto the plurality of contacts; and a common contact made of a conductive resin material and configured to electrically connect the plurality of ground contacts together among the plurality of contacts. The plurality of contacts integrated together by the supporting member are received in the receiving space.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: May 15, 2012
    Assignees: Yamaichi Electronics Co., Ltd., Yamaichi Electronics USA, Inc.
    Inventors: Toshiyasu Ito, Donald Eric Thompson, Takeshi Nishimura
  • Publication number: 20090168905
    Abstract: An embodiment of the invention is directed to a system for processing a plurality of encoded signals carrying data. The system includes an electronic circuit configured to receive the encoded signals from one or more external devices, wherein the data are encoded in the encoded signals according to one or more of a plurality of protocols. The system further includes a processor configured to receive the encoded signals from the electronic circuit, and to extract the data from the encoded signals by decoding the encoded signals. The processor is configured to perform decoding according to the plurality of protocols.
    Type: Application
    Filed: March 13, 2008
    Publication date: July 2, 2009
    Inventors: Donald Eric Thompson, David Wayne Stonely
  • Patent number: 6939175
    Abstract: A coaxial cable for transmitting high frequency signals includes includes a body having a center conductor and a shield formed coaxially around the center conductor and separated from the center conductor by a layer of dielectric having an annular layer of electro-static-discharge polymer. The cable also includes conductive pads to engage contacts on a mating connector. At least one of the conductive pads is attached to the center conductor and at least another one of the conductive pads is attached to the shield.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: September 6, 2005
    Assignee: Teradyne, Inc.
    Inventors: Frank Parrish, Arash Behziz, Derek Castellano, Arthur E. LeColst, Donald Eric Thompson, Jonathan M. Becker
  • Publication number: 20030122538
    Abstract: A tester interface assembly is disclosed for coupling a plurality of tester electronic channels to a device-interface-board. The tester interface assembly includes at least one harness assembly having a plurality of coaxial cables, each cable including a body having a center conductor and a shield. The shield is formed coaxially around the center conductor and separated therefrom by a layer of dielectric. Each cable further includes a distal tip formed substantially similar to the body and including respective formed conductive pads disposed on the distal extremities of the center conductor and the shield. The harness employs a housing formed with an internal cavity for receiving and securing the cable distal ends in close-spaced relationship such that the distal tips form an interface engagement plane. A compliant interconnect is interposed between the harness assembly and the device-interface-board, and includes a plurality of conductors formed to engage the cable distal ends along the engagement plane.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 3, 2003
    Applicant: Teradyne, Inc.
    Inventors: Frank Parrish, Arash Behziz, Derek Castellano, Arthur E. LeColst, Donald Eric Thompson, Jonathan M. Becker
  • Patent number: 6515499
    Abstract: A tester interface assembly is disclosed for coupling a plurality of tester electronic channels to a device-interface-board. The tester interface assembly includes at least one harness assembly having a plurality of coaxial cables, each cable including a body having a center conductor and a shield. The shield is formed coaxially around the center conductor and separated therefrom by a layer of dielectric. Each cable further includes a distal tip formed substantially similar to the body and including respective formed conductive pads disposed on the distal extremities of the center conductor and the shield. The harness employs a housing formed with an internal cavity for receiving and securing the cable distal ends in close-spaced relationship such that the distal tips form an interface engagement plane. A compliant interconnect is interposed between the harness assembly and the device-interface-board, and includes a plurality of conductors formed to engage the cable distal ends along the engagement plane.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 4, 2003
    Assignee: Teradyne, Inc.
    Inventors: Frank Parrish, Arash Behziz, Arthur E. LeColst, Derek Castellano, Donald Eric Thompson, Jonathan M. Becker