BACKGROUND 1. Field The present invention relates to an improved method and structure for forming an electrical interconnect mechanism in a Power Distribution Network (PDN) in which the present invention maintains stable power supplies at their target voltage across an entire usage range of a device under test (DUT) or circuit. The PDN is an entire network between the power supply and the DUT. In particular, the present invention provides and places capacitors on the printed circuit board (PCB) of the structure to decouple the PDN and result in lower impedance benefitting the frequency range of the PDN to effect a significant performance improvement in the spring-pin inductance from the transmission line. This reduction in impedance results in a reduction of the power supply ripple.
2. The Prior Art U.S. Pat. No. 6,597,190 to Chan et al. relates to an apparatus for testing electronic devices. This patent requires that the spring-pin has a shoulder and that it sits on top of the board to make a connection. In addition, the Chan et al. patent discloses in its drawings that the power and ground planes are located in the wider part of the pin area.
In addition, the Chan et al. patent shows the board (element 320) on the bottom of the socket. In Chan et al., the capacitors are placed and located on the bottom which significantly reduces the benefit you get from having capacitors on the socket at all. Other elements in the Chan patent include a plurality of pins 155, the contactor housing 310, the power plane 360 and the ground plane 370 and, the test contactor 305. There is little to no advantage from just placing the capacitors on the board into which the socket is plugged.
SUMMARY The present invention provides for an improved method and structure for forming an electrical interconnects mechanism in a Power Distribution Network (PDN). The present invention provides and places capacitors on the printed circuit board (PCB) of the structure to decouple the PDN and result in lower impedance benefitting the frequency range of the PDN to effect a significant performance improvement in the spring-pin inductance from the transmission line. This reduction in impedance results in a reduction of the power supply ripple. This is accomplished by placing the capacitors on the top of the pin array. The loop inductance of having the capacitor on the top side provides for a much better result than having the capacitors on the bottom of the pin as noted in the aforementioned prior art proposal. By placing the capacitors on the bottom, the inductance of the spring-pins are added to the inductances. This significantly negates or arguably removes the benefit and cost of putting these capacitors on the socket.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a prior art illustration of the location of capacitors on the bottom of a printed circuit board (PCB);
FIG. 1B illustrates capacitors are placed on top of a pin array on a printed circuit board (PCB) in accordance with the teachings of the present invention;
FIG. 2 illustrates a loop inductance in which capacitors are placed on top of the pin array as shown in FIG. 1B;
FIG. 3A is a prior art illustration referencing a prior art illustration in FIG. 1 of the Chan patent in which a spring pin has a shoulder that rests or is seated on top of a printed circuit board (PCB);
FIG. 3B shows an alternative to the prior art approach of FIG. 3A in which a plated inner hole for a pin that touches or makes contact with the plating as it is held in place through the use of a top narrow plunger-like electrical connection permitting the use for fine pitch solutions of approximately 0.4 mm and 0.35 mm pitch sockets in accordance with the teachings of the present invention;
FIG. 4A illustrates both the configuration of the present invention in which capacitors are located on top of a socket of a printed circuit board (PCB) and also the prior art proposal in which capacitors are on a bottom of a socket of a printed circuit board (PCB);
FIG. 4B is a graph illustrating impedance and frequency for capacitors placed on top of a socket of a printed circuit board (PCB) as shown in FIG. 4A;
FIG. 4C is a chart showing the values plotted for the graph in FIG. 4B;
FIG. 5A shows a prior art proposal for power and ground planes in a socket for a 0.35 mm pitch;
FIG. 5B shows an embodiment of the present invention in which room is provided to build power and ground planes in a fat or wide portion of the hole for the tolerance to work;
FIGS. 6A-6G show the methodology steps of the present invention in which:
FIG. 6A shows etching power ground planes at atop of a socket;
FIG. 6B shows the drill stepped hole;
FIG. 6C shows a plate via;
FIG. 6D shows the step of removing top copper on the power ground plane;
FIG. 6E shows the step of routing in the power planes;
FIG. 6F shows a step of adding the pins; and
FIG. 6G shows the completely assembled structure of the present invention;
FIG. 7 shows capacitor placement in accordance with the teachings of the present invention;
FIG. 8A shows the pins prior to placement in said power or ground planes in said holes or openings; and
FIG. 8B shows the pins after placement within said power or ground planes in said holes or openings;
FIG. 9A is a chart of values for different sized vias having a fat or wide portion of said holes to accommodate or house power and ground planes within a range of tolerances for pitch sockets in said fat or wide portion of said holes;
FIG. 9B shows the top view where a plunger drill widens a drilled via for placement in the wider portion of power or ground planes in the vias and to house pitch sockets of various sizes as described but not limited to the sizes shown in FIG. 9A; and
FIG. 9C shows a side view where a plunger drill widens a drilled or barrel drilled via 16d for placement in the wider portion of power or ground planes in the plated and non plated holes 16a, 16b, respectively and to house pitch sockets of various sizes as described but not limited to the sizes shown in FIG. 9A.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) Referring now to the drawings, FIG. 1A is a prior art illustration of the location of capacitors on the bottom of a printed circuit board (PCB) as shown in U.S. Pat. No. 6,597,190 to Chan et al. The Chan et al. patent shows the PCB (element 320) on the bottom of the socket. In Chan et al., the capacitors are placed and located on the bottom which significantly reduces the benefit you get from having capacitors on the socket at all. There is little to no advantage from just placing the capacitors on the board for plugging into the socket.
FIG. 1B illustrates a portion of the structure and methodology of the present invention in which capacitors 5 are placed on top of a pin array 8 on a printed circuit board 10 (PCB) in accordance with the teachings of the present invention. The purpose of having capacitors in the socket is to reduce the inductance between the capacitors and the device under test 11 (DUT) which is connected or placed on top of the PCB. By placing the capacitors on the bottom, the benefit derived from having capacitors on the socket is significantly reduced and the capacitors might just as well be put into the board in which the socket is plugged.
FIG. 2 illustrates a loop inductance in which capacitors are placed on top of the pin array as shown in FIG. 1B. In FIG. 2, the loop inductance provides a much better result with the present invention's solution of placing capacitors 5 on top than by having the capacitors 5 on the bottom of the pin array 8. By placing the capacitors 5 on the bottom, as taught in the aforementioned prior art reference, means that the inductance of the spring-pin 5 is added to the loop inductance significantly negating and possibly removing the benefit and cost of putting the capacitors 5 on the socket 12.
FIG. 4A illustrates both the configuration of the present invention in which capacitors are located on top of a socket 12 of a printed circuit board 10 (PCB) and also the prior art proposal in which capacitors are on the bottom of a socket of a printed circuit board (PCB). The advantages can be seen in FIGS. 4B and 4C. FIG. 4B is a graph illustrating impedance and frequency for capacitors placed on top of a socket of a printed circuit board (PCB) as shown in FIG. 4A. FIG. 4C is a chart showing the values plotted for the graph in FIG. 4B and the reduction in power supply ripple when the capacitors are placed on top of the socket.
As can be seen from FIGS. 4B and 4C, the present invention provides better lower impedance and by adding capacitance 5 in the socket 12 and shows PDN benefits in the intended frequency range of approximately 5 MHz to 500 MHz. This improvement is affected by changing the location of the capacitors to be placed on top of a socket 12 of a printed circuit board 10 (PCB) resulting in improved performance in the critical frequency range of approximately 5 MHz to 500 MHz. In the approximate range of 5 MHz to 500 MHZ, there is a significant improvement since the present invention structure and methodology eliminates a majority of spring pin inductance from the transmission line. From a practical standpoint, this reduction in impedance results in a reduction of power supply ripple as shown in FIG. 4C. FIG. 4C shows a constant improvement of 65% in the aforementioned target frequency range. A 65% improvement means that a 100 mV ripple on a power line supply would become 35 mV simply by changing the location of the capacitors from the bottom to the top of the socket.
FIG. 3A is a prior art illustration described in the aforementioned Chan patent in which a spring pin 340 has a shoulder (see FIG. 1 of prior art illustration in Chan patent, element 160) that rests or is seated on top of a printed circuit board 370 (PCB). Other elements in the Chan patent description include ground pin 340, lip 162 of the ground pin 340 and the beveled tip 164, aperture 372, and ground plane 370. FIG. 3B shows an alternative to the prior art approach of FIG. 3A in which a plated inner hole 16a for a pin 8 that touches or makes contact with the plating 16a as it is held in place permitting a use of a top narrow plunger-like electrical connection 8a. The top narrow plunger 8a allows fine pitch solutions of approximately 0.4 mm and 0.35 mm pitch sockets in accordance with the teachings of the present invention. The shoulder that rests or is seated on top of a printed circuit board, see shoulder element 160 of FIG. 1 of the Chan patent showing a prior art proposal, requires greater mechanical space and is unsuitable for 0.4 mm and 0.35 mm sockets.
FIGS. 5A and 5B compare the prior art and the present invention, respectively, for power and ground planes 18 in a socket for a 0.35 mm pitch. FIG. 5B is an embodiment of the present invention where room is provided to build power and ground planes in a fat or wide portion of the plated hole 16a and the non plated hole 16b, respectively for the tolerance to work.
FIGS. 6A-6G show the methodology steps of the present invention. FIG. 6A describes the etching of the power and/or ground planes at a top surface of a socket. Next a stepped hole is drilled as shown in FIG. 6B. The drilled via 16d is then plated, preferably with a dielectric such as copper 16c, as shown in FIG. 6C to become a plated hole 16a. The holes 16a, 16b have room, with a “hole to copper” tolerances of 2.5 mils to 5 mils to allow for a minimum copper thickness of no smaller than 1.8 mils in between the via 16d and the hole 16a, 16b so that the plated copper area 16ca forms a keep out hole 16c. Next the copper from the top is removed for the power and/or ground planes as shown in FIG. 6D. The power and/or ground plans are then routed as shown in FIG. 6E FIG. 6F shows the step of adding pins in the power or ground planes. The completed structure is shown in FIG. 6G.
FIG. 7 shows capacitor placement within the surface of the socket in accordance with the teachings of the present invention. Cutouts under the frame allow for the capacitors to be placed on the surface of the socket. The capacitors are installed using standard PCB assembly process in a panel. The process steps are etching copper or conductive material on PCB, coating or plating copper surface to prevent oxidation and promote adhesion of solder, applying solder-mask to restrict solder flow, applying solder-paste at capacitor pads, pick-and-place capacitors on board, and melting solder-paste in a reflow oven and with typical solder temperature profiles.
This provides for an advantage in applications where it is important that power net ripple is low. Many devices that have challenging PI requirements are integrated circuits (ICs) for use in mobile phones, tablets, and laptops. These devices often have small Ball Grid Array (BGA) pitches of 0.35 mm 0.4 mm and therefore are critical for the mobile market segment. The socket must have an individual contact for each BGA pad so it must also be match the same pitch as the device going into the socket.
FIG. 8A shows the pins 6 prior to placement in said power or ground planes in said holes or openings. FIG. 8B shows the pins after placement within said power or ground planes in said holes or openings. The holes or vias have room, with a “hole to copper” tolerances of 2.5 mils to 5 mils to allow for a minimum copper thickness of no smaller than 1.8 mils in between the via or opening and the hole so that the plated copper area forms a keep out hole. The hole to copper is the distance between a plated hole 16a or non plated hole 16b and a via 16d and a copper feature on a PCB.
FIG. 9A is a chart of values for different sized holes 16b having a fat or wide portion of dielectric in between said holes 16a. The holes 16a, 16bb accommodate and capture one end of a spring pin. The fat or wide portion of said dielectric 16c accommodates power and ground planes within a range of tolerances for 0.35 mm, 0.4 mm, 0.5 mm, 0.65 mm, 0.8 mm, and 1.0 mm pitch socket hole patterns.
FIG. 9B shows the top view where a copper plane is pulled back and electrically isolated from 3 holes and electrically connected to 1 hole.
FIG. 9C shows a side view of an array of two stepped holes. Holes 16b have no copper plating whereas holes 16a have copper plating that electrically connects to copper planes. The holes 16b and vias 16a capture the spring pin plunger where a plated hole 16a enables electrical connection of said via to electrically connect to a copper plane. The plating in the holes 16a also enable electrical connection of spring pins to copper planes. Unplated holes 16b capture the spring pins but do not electrically connect to copper planes.
The fat or wide dielectric 16c in between two holes or vias accommodates the copper plane to pass through the array, listed as copper web. Reasonable manufacturing tolerances for said copper web are listed in FIG. 9A.
While presently preferred embodiments have been described for purposes of the disclosure, numerous changes in the arrangement of method steps and apparatus parts can be made by those skilled in the art. Such changes are encompassed within the spirit of the invention as defined by the appended claims.
