Abstract: A method is presented for creating a fully-aligned via (FAV) by employing selective metal deposition. The method includes forming metal lines within a first inter-layer dielectric (ILD) layer, forming a second ILD layer over the first ILD layer, forming a lithographic stack over the second ILD layer to define areas where via growth is prevented, recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack, and performing metal growth over the exposed top surface of the metal lines where via growth is permitted.

Abstract: A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers.

Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.

Abstract: Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow.

Abstract: A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the metal-containing structure. The composite capping layer includes a manganese-containing layer disposed over the metal-containing structure, a silicon-containing low-k dielectric layer disposed over the manganese-containing layer, and an intermediate layer between the manganese-containing layer and the silicon-containing low-k dielectric layer. The intermediate layer is the reaction product of the manganese-containing layer and the silicon-containing low-k dielectric layer.

Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

Abstract: A method is presented for post chemical mechanical polishing (PCMP) clean for cleaning a chemically-mechanically polished semiconductor wafer. The method includes planarizing the semiconductor wafer, subjecting the semiconductor wafer to a de-oxygenated mixture of DI water and PCMP solution, and applying a de-oxygenated environment during the cleaning. The solution can be de-oxygenated by nitrogen degas or by introducing a reducing agent. The environment can be de-oxygenated by purging with an inert gas, such as nitrogen.

Abstract: A method is presented for post chemical mechanical polishing (PCMP) clean for cleaning a chemically-mechanically polished semiconductor wafer. The method includes planarizing the semiconductor wafer, subjecting the semiconductor wafer to a de-oxygenated mixture of DI water and PCMP solution, and applying a de-oxygenated environment during the cleaning. The solution can be de-oxygenated by nitrogen degas or by introducing a reducing agent. The environment can be de-oxygenated by purging with an inert gas, such as nitrogen.

Abstract: Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow.

Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.

Abstract: A method is presented for forming a semiconductor device. The method includes depositing a sacrificial layer on a fin structure formed on a substrate and then filled with polysilicon, etching a portion of the polysilicon material via a first etching process, and pre-cleaning the surface native oxide layer. The method further includes etching the remaining polysilicon material via a second etching process, and removing polysilicon etch residue formed adjacent the fin structure by a cleaning process. The pre-cleaning is performed by applying ammonia (NH3) and nitrogen trifluoride (NF3) or by applying buffered hydrofluoric acid (BHF). The first etching process is reactive ion etching (RIE) and the second etching process involves applying nitrogen trifluoride (NF3) and hydrogen gas (H2).

Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

Abstract: A method is presented for forming a semiconductor device. The method includes depositing a sacrificial layer on a fin structure formed on a substrate and then filled with polysilicon, etching a portion of the polysilicon material via a first etching process, and pre-cleaning the surface native oxide layer. The method further includes etching the remaining polysilicon material via a second etching process, and removing polysilicon etch residue formed adjacent the fin structure by a cleaning process. The pre-cleaning is performed by applying ammonia (NH3) and nitrogen trifluoride (NF3) or by applying buffered hydrofluoric acid (BHF). The first etching process is reactive ion etching (RIE) and the second etching process involves applying nitrogen trifluoride (NF3) and hydrogen gas (H2).

Abstract: A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers.

Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

Abstract: A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the metal-containing structure. The composite capping layer includes a manganese-containing layer disposed over the metal-containing structure, a silicon-containing low-k dielectric layer disposed over the manganese-containing layer, and an intermediate layer between the manganese-containing layer and the silicon-containing low-k dielectric layer. The intermediate layer is the reaction product of the manganese-containing layer and the silicon-containing low-k dielectric layer.

Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

Abstract: A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the metal-containing structure. The composite capping layer includes a manganese-containing layer disposed over the metal-containing structure, a silicon-containing low-k dielectric layer disposed over the manganese-containing layer, and an intermediate layer between the manganese-containing layer and the silicon-containing low-k dielectric layer. The intermediate layer is the reaction product of the manganese-containing layer and the silicon-containing low-k dielectric layer.